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| - | courses:ee6361_2019:start [2019/01/25 10:42] janakiraman [Class 1 (18 Jan 2018)] |
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| + | Previous revision |
| + | courses:ee6361_2019:start [2019/04/23 10:29] (current) janakiraman [Class 13 (12 Apr 2019)] |
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| * Flip flop | |
| * 6T SRAM basics | |
| ===== Class 2 (25 Jan 2019) ===== | |
| * 6T SRAM cell | |
| * Static/ Read and Write noise margins | |
| * Read/ Write/ Hold and Access failures | |
| * Column interleaving | |
| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE6361/Jan-2019/material/20190125_IITM_C1.pdf|Lecture Slides]] | |
| ===== Class 3 (1 Feb 2019) ===== | |
| * Alternative Cell Types | |
| - Split word line with single ended read | |
| - Assymetric cells | |
| - Decouple Read/Write Cells (8T Cells) | |
| - Regenerative Feedback | |
| * Impact of Variation | |
| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE6361/Jan-2019/material/20190201_IITM_SRAM_C2.pdf|Lecture Slides]] | |
| ===== Class 4 (8 Feb 2019) ===== | |
| * Redundancy | |
| * Modes of failure | |
| * Assist Circuits | |
| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE6361/Jan-2019/material/20190208_IITM_SRAM_C3.pdf|Lecture Slides]] | |
| ===== Class 5 (15 Feb 2019) ===== | |
| * BTI Stress | |
| * Memory Testing | |
| * Power | |
| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE6361/Jan-2019/material/20190215_IITM_SRAM_C4.pdf|Lecture Slides]] | |
| ===== Class 6 (22 Feb 2019) ===== | |
| * Variation characterization | |
| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE6361/Jan-2019/material/20190222_IITM_SRAM_C5.pdf|Lecture Slides]] | |
| ===== Class 7 (1 Mar 2019) ===== | |
| * Variation characterization (continued ...) | |
| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE6361/Jan-2019/material/20190301_IITM_SRAM_C6.pdf|Lecture Slides]] | |
| ===== Class 8 (8 Mar 2019) ===== | |
| * Course project description - In Memory Computing | |
| ===== Class 9 (15 Mar 2019) ===== | |
| * Basics of DRAM | |
| * Definition of Embedded | |
| * Requirement for short BLs in DRAMs | |
| * Transfer ratio | |
| * Retention time/ Refresh rate analysis | |
| * Power supplies required for eDRAM | |
| * Advantages of eDRAM over eSRAM | |
| [[https://goo.gl/forms/FG3QAKgnXLlHb4bB3|In class Quiz]] | |
| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE6361/Jan-2018/material/EE6361-eDRAM-Janakiraman-2018.pdf|eDRAM Lecture Slides (2018)]] | |
| ===== Class 10 (22 Mar 2019) ===== | |
| * Write time calculation | |
| * Hierarchical sensing | |
| * 3T Micro Sense Amp | |
| * Micro Sense Amp Evolution | |
| Barth, J. et al., “A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008. [[http://ieeexplore.ieee.org/document/4443182/|PDF]] | |
| [[https://forms.gle/7fZHaL8i231yZ9VW7|In class quiz]] | |
| ===== Course Project ===== | |
| **SRAM based In Memory Compute circuit design to implement the Multiply Accumulate Operation** | |
| ==== Reference papers ==== | |
| - A. Biswas and A. P. Chandrakasan, "CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks," in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 217-230, Jan. 2019. doi: 10.1109/JSSC.2018.2880918 | |
| - M. Kang, S. K. Gonugondla, A. Patil and N. R. Shanbhag, "A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array," in IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 642-655, Feb. 2018. doi: 10.1109/JSSC.2017.2782087 | |
| ===== Class 11 (29 Mar 2019) ===== | |
| * Read time calculation | |
| * SOI Technology - Floating body effects on eDRAM | |
| * Gated Feedback Sense Amplifier | |
| G. Fredeman et al., "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. | |
| doi: 10.1109/JSSC.2015.2456873 [[https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7210238|PDF]] | |
| [[https://forms.gle/8de7B43mobrrEb7A9|In class quiz]] | |
| ===== Class 12 (5 Apr 2019) ===== | |
| * Variability study | |
| * Thick Oxide Word-line drivers | |
| * Thin Oxide Word-line drivers | |
| [[https://forms.gle/9Y1RgQBuT4qiugpH7|In class quiz]] | |
| ===== Class 13 (12 Apr 2019) ===== | |
| * Redundancy and Testing | |
| * Non Volatile Memories | |
| * Charge Trap Transistor | |
| [[https://forms.gle/7NgWNBcYsndjrwSy6|In class quiz]] | |
| Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian Iyer 80Kb Logic Embedded High-K Charge Trap Transistor based Multi-Time-Programmable Memory with no Added Process Complexity J. Solid State Circuits,53(3): 949-960 (2018) [[https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8252917&tag=1|PDF]] | |
| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE6361/Jan-2019/material/eNVRAM_Talk_at_IISc_Sep26_v15.pdf|eNVM Lecture Slides ]] | |