• Saurabh Saxena

• Online

• Tue./Thu.: 4:00-5:15 PM
• Alternate Friday

Registered students can login and see the course page at https://courses.iitm.ac.in/. Resources, tutorials, exam schedules, discussion forum etc. can be accessed from the moodle page.

Login to moodle at https://courses.iitm.ac.in/ to post questions and contact faculty.

• Assignments (10%)
• Quiz-I (20%)
• Quiz-II (20%)
• Project (20%)
• End Sem (30%)

The recorded lectures are listed below.

Assignments will be posted below. You are expected to solve them on your own. You should submit each one by 09:00AM of the due date mentioned. Copying will carry strict penalties.

Topics include analog and digital integer-N phase-locked loops (PLLs). Building blocks include phase/frequency detectors, charge-pump, LC/ring-oscillators, multi-modulus frequency dividers, active/passive loop-filter, etc.

To develop intuition behind frequency synthesizer design, learning mathematical basis behind operation, and realizing PLLs at architecture and transistor level.

• F. Gardner, Phaselock Techniques, John Wiley & Sons, 2005.
• W. Egan, Phase-Lock Basics, John Wiley & Sons, 2008.
• R. Best, Phase-Locked Loops : Design, Simulation, and Applications, McGraw Hill, 2003.

• Analog Circuits

Attendance will be strictly enforced.