When the gate is connected to the resistive voltage divider, some students found that the divider tap voltage changes, implying a current that is flowing from the gate. This problem was worse when the experiment was done with higher values of V_cc

In addition to the inverter we are using, there are five more, whose inputs are floating, and protection diodes to V_cc and gnd pins at each input. The floating inputs get biased near V_cc/2 because of the divider formed by protection diodes. (This voltage can in fact be measured with a voltmeter)

When the floating inputs are biased in this way, the inverters tend to have a current flowing through them, which flows back to the input of the inverter that we are using through the protection diode. This can be verified by measuring the voltage at the gnd pin of the IC. At higher V_cc, the inverter's crowbar current is higher, leading to larger shifts in voltage.

Connect the unused inputs to gnd pin of the IC to ensure that the unused inverters have zero current through them. (Do this in both nMOS and pMOS measurements so that the problem doesn't occur)

It most likely does, but the particular combination of bias voltages could be such that the resulting current is very small.