About me:

1. I am a MS student of Electrical Engineering in VLSI group of IIT Madras, Chennai.
2. I design analog circuits.

Projects

1. Designed front end of a thermocouple signal conditioner.
2. Worked on obtaining memoryless conversion using ΔΣ ADC without using reset.

Publications

1. Debasish Behera, Nagendra Krishnapura, “A 2-Channel 1MHz BW, 80.5 dB DR ADC using ΔΣ modulator and zero-ISI filter,” To appear in ESSCIRC-2014.
2. Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Debasish Behera, Nimit Nigania, “A 16 MHz BW 75 dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay,” IEEE Journal of Solid-State circuits, vol. 47, no. 8, pp. 1884-1895, Aug. 2012.
3. Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera “A 16 MHz BW 75 dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay,”Proc. of 2011 CICC, San Jose, Sep. 2011.