I am Chithra, a post-doctoral researcher under Dr. Saurabh Saxena. My research interest include design of low-power, compact clocking solutions to mixed-signal ICs, time-to-digital converters (TDCs), digital-to-time converters (DTCs), delay-locked loops (DLLs) and phase-locked loops(PLLs). I am currently designing a TDC for quantum key distribution (QKD) system. 
Prior to this, I completed my Ph.D. under the guidance of Prof. Nagendra Krishnapura.   During my Ph.D., we designed and tested a compact, low power, 18-channel TDC in 130nm CMOS process for the iron calorimeter detector in the India-based neutrino observatory (INO). We also proposed two techniques to suppress static phase offset in DLLs, a nonideality that affects the linearity of high-resolution single-shot TDCs.

====== Publications  ======
===== Journals =====
  - Chithra, A. Narayanan, R. S. A. Kumar and N. Krishnapura, "Auto-zeroing Static Phase Offset in DLLs using a Digitally Programmable Sensing Circuit," in// IEEE Transactions on Circuits and Systems II: Express Briefs//, doi: 10.1109/TCSII.2021.3049134.
  - Chithra and N. Krishnapura, "A flexible 18-channel multi-hit time-to-digital converter for trigger-based data acquisition systems," in //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 67, no. 6, pp. 1892-1901, Jun. 2020, doi: 10.1109/TCSI.2020.2969977.
  - Chithra, P. S and A. A. Prince, "RF MEMS-based biosensor for pathogenic bacteria detection," //BioNano Science//, vol. 3, no. 3, pp. 321-328, Sep. 2013, doi: 10.1007/s12668-013-0098-1.

===== Conferences =====
  - Chithra, "A technique for measuring picosecond delays using phase modulation", //accepted for poster presentation in 2021 IEEE International Symposium on Circuits and Systems (ISCAS)//.
  - Chithra and N. Krishnapura, "Static phase offset reduction technique for delay locked loops," //2019 IEEE International Symposium on Circuits and Systems (ISCAS)//, Sapporo, Japan, 2019, pp. 1-5, doi: 10.1109/ISCAS.2019.8702613.
  - Chithra and N. Krishnapura, "Modeling techniques for faster verification of a time-to-digital converter system-on-chip design," //2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)//, Hyderabad, India, 2019, pp. 1-6, doi: 10.1109/MOS-AK.2019.8902447.

====== Patents ======
  - 	N. Krishnapura, Chithra, A. Narayanan and R. S. A. Kumar, "Static phase offset reduction in DLLs using a digitally programmable sensing circuit," India patent application #202041057083. (Patent pending).