| MS Seminar

Name of the Speaker: Ms. KEERTHANA RAMESH (EE23S036)
Guide: Dr. Shanthi Pavan
Venue: ESB-244 (Seminar Hall)
Date/Time: 17th October 2025 (Friday), 11:00 AM
Title: A MATLAB-based toolbox for CTP ADCs and its application to the design of a filtering SAR-ADC driver.

Abstract :

Continuous-time pipeline (CTP) analog-to-digital converters (ADCs) are a relatively recent architecture whose design and analysis require careful understanding. The developed toolbox provides an aid for exploring the CTP architecture, enabling rapid first-cut analysis and design choices.Traditional Cadence simulations such as transient Monte Carlo and noise analysis are often time-consuming; the proposed toolbox allows faster block-level simulations of CTP ADCs.

High-precision ADCs such as successive-approximation (SAR) converters typically present a large input capacitance, necessitating a power-hungry buffer to drive the switched-capacitor load. The CTP architecture eliminates this buffer, offering a low-power alternative. In addition, it improves signal-to-noise ratio (SNR) by a factor of 20log(G), thereby enhancing overall ADC performance. The toolbox’s capabilities are demonstrated through the design of a filtering SAR driver implemented in TSMC 65 nm CMOS technology.