| MS TSA Meeting

Name of the Speaker: Mr. Narala Raghavendra Reddy (EE17S039)
Guide: Dr. Sankaran Aniruddhan
Online meeting link: http://meet.google.com/ahd-kwpk-rbr
Date/Time: 23rd September 2025 (Tuesday), 10:00 AM
Title: Dual Slope DTC based Low Jitter Fractional output dividers with non-linearity Compensation.

Abstract :

Open-loop Fractional Output Dividers (FOD), which are implemented using a DTC (Digital to Time Converter), are gaining popularity but suffer from non linearities due to effects of mismatches etc. This paper presents a memoryless 12- bit dual-slope DTC architecture with on-chip Gain & Integral Non-Linearity (INL) calibration to compensate for the non-linearities present in delay generation. The proposed DTC is implemented in a 65 nm CMOS process, and a 100 fs resolution is achieved for approximately 400 ps range (corresponding to an input frequency of 2.5 GHz). The measured Total Jitter on the chip are 220 fsrms & 135 fsrms for pre- & post-correction respectively, at an output frequency of 156.25 MHz. This includes a random rms jitter of 50 fs from the input 2.5 GHz clock.