| PhD Seminar

Name of the Speaker: Mr. Nishanth A B (EE20D701)
Guide: Dr. Shanthi Pavan
Venue: ESB-244 (Seminar Hall)
Online meeting link: https://meet.google.com/vqe-omdx-xnd
Date/Time: 1st Aug 2025(Friday), 10 AM
Title: Design, Characterization, and Calibration of Continuous-Time Pipelined Analog to Digital Converters

Abstract :

The Continuous-Time Pipelined (CTP) ADC architecture offers a fundamental advantage over traditional ADCs in terms of noise performance and linearity. However, being a relatively recent development, it still faces several practical implementation challenges.

This work addresses several of these challenges and presents key innovations that enable robust and efficient CTP operation. These include: 1. A startup-time calibration technique for dynamically generating reconstruction filters across temperature variations. 2. Innovations to mitigate saturation due to full-scale alias-band inputs 3. DAC mismatch calibration technique that achieves a 33% reduction in digital reconstruction power. The proposed solutions are demonstrated through a three-stage CTP ADC that achieves 12-bit resolution over a 100 MHz bandwidth. The design was fabricated in 65 nm CMOS technology with a 1.2 V supply and consumes approximately 60 mW of power. The measured Schreier Figure of Merit (FOM) is 165.2 dB, validating the efficacy of the proposed architecture.