| MS Seminar

Name of the Speaker: Mr. RAJ SURYA (EE21S123)
Guide: Dr. Radha Krishna Ganti
Online meeting link: http://meet.google.com/jze-jzvm-jyv
Date/Time: 6th August 2025 (Wednusday), 11:00 AM
Title: IMPLEMENTATION OF AN OPTIMISED TRANSMITTER CHAIN FOR 5G-NR MASSIVE MIMO SYSTEMS.

Abstract :

In a growing world of wireless communications, massive MIMO plays a crucial role in offering very high data rates, reduced latency and improved system performance. For such systems, the transmitter chain should be robust enough to mitigate these features. My work concentrates on implementing signal processing algorithms and optimizing them for the MIMO transmitter chain, which emphasizes building long listed modules’ like transport block processing, code block processing, source encoder (LDPC for PDSCH and Polar codes for SSB and PDCCH) , scrambler, user and bit interleavers followed by resource grid mappers with multiple layered transmissions and adaptive modulation (BPSK, M-QAM schemes). The approach followed in implementing these algorithms can be improved by using FPGA accelerator cards, but the software architecture should also be on par with the FPGA resources for a sound performance. Implementation of such complex algorithms on an FPGA should be planned prior to leverage the resources better. Optimisation at the modular level is needed to meet the physical resource requirements and 3GPP standards requirements by keeping a track on timing analysis. The proposed architecture is supported by mmWave systems also with precise timing evaluations. With this architecture, a throughput of around 200Mbps and 1.25 Gbps is observed for a SISO and four layered MIMO downlink transmission respectively. The architecture is flexible enough to scale up and down based on the number of MIMO layers and is capable of handling up-to 30 users per slot. Verification and validation of the architecture is done using matlab results adhered to standard specifications.