| PhD Seminar

Name of the Speaker: Mr. Ajay Kumar Rai (EE21D024)
Guide: Dr. Kamalesh Hatua
Online meeting link: https://meet.google.com/xxf-qsrc-sjt
Date/Time: 9th July 2025(Wednesday), 11 AM
Title: Mitigating Voltage Imbalance During Body Diode Turn-Off in Series-Connected SiC MOSFET-Based Power Converters

Abstract :

High-voltage wide bandgap (WBG) devices, particularly SiC MOSFETs, have the potential to transform medium-voltage (MV) power conversion by offering lower switching losses, improved thermal performance, and higher blocking voltages compared to silicon devices. However, commercially available SiC MOSFETs lack sufficient voltage blocking capability for many MV applications, while high-voltage (10 kV/15 kV) SiC MOSFETs remain costly and limited in availability. Cascaded multilevel converters address voltage limitations using low-voltage devices but at the expense of increased complexity, cost, and reduced power density.

An alternative approach is to connect commercially available SiC MOSFETs in series to meet MV blocking requirements, enabling simpler, more compact converter designs with higher power density. However, this strategy introduces the challenge of dynamic voltage imbalance across series-connected MOSFETs, particularly during turn-off events, which can lead to device overvoltage and failure. While active and passive voltage balancing techniques for MOSFET turn-off are well studied, the issue of voltage imbalance during body diode turn-off remains largely unexplored.

This talk presents an active voltage balancing technique for body diode turn-off in series-connected SiC MOSFETs, using active gate drivers to regulate gate charge during voltage transients, ensuring uniform voltage sharing among body diodes. It will cover modeling, practical implementation, and experimental results with two series-connected SiC MOSFETs in a half-bridge converter configuration, operating in buck and sinusoidal modes at a 1.5 kV DC bus voltage with switching frequencies up to 40 kHz.