| PhD Seminar

Name of the Speaker: Mr. Balaji Vijayakumar (EE19D202)
Guide: Dr. Janakiraman Viraraghavan
Venue: ESB-244 (Seminar Hall)
Date/Time: 19th May 2025 (Monday), 11 AM
Title: A 28nm SRAM-Based Compute-In-Memory Macro Supporting 2-to-10 Bit Output Precision with Input-Conditioned and Full-Range Quantization

Abstract :

Edge-based artificial intelligence (AI) inference tasks have kindled significant interest in non-von Neumann architectures like Compute-In-Memory (CIM). A fundamental operation in analog CIM engines is the multiply-and-accumulate (MAC) operation performed per memory column, which is quantized by an analog-to-digital converter (ADC). For macros supporting MAC lengths of up to 1024, AI workloads demand a broad range of MAC precisions. However, constructing a high-precision ADC is expensive due to pitch-matching constraints in a CIM setting. To address this, we propose a hardware technique that leverages a 7-bit on-chip ADC to achieve up to 10-bit precision. This is accomplished through two modes of operation: full-range quantization (FRQ) and input-conditioned quantization (ICQ). FRQ operates the ADC over fewer cycles to support 2-to-7-bit precision. For >7 bits, ICQ is employed, where the reduced MAC range, conditioned on an input, is mapped to the ADC's dynamic range using residue amplification. The proposed ICQ and FRQ approaches offer tunable knobs to optimize MAC range mapping enabling enhanced energy efficiency and sparsity control. Specialized calibration techniques are shown to handle mismatches in the residue amplifier circuitry. A 424Kb SRAM-based CIM macro fabricated in TSMC 28nm achieves 196.6-to-102 tera-operations per second per watt per bit (TOPS/W/b) energy efficiency across 2-to-10 bits, with <1 % accuracy loss on MNIST, CIFAR-10, and CIFAR-100.