| PhD Seminar

Name of the Speaker: Mr. Prashant Singh (EE18D026)
Guide: Dr. Karmalkar S
Co-Guide: Dr. Ananth Krishnan
Online meeting link: https://meet.google.com/soy-xhaa-fyg
Date/Time: 21st April 2025 (Monday), 9:00 AM
Title: Design of SiC MOSFET to Improve Short Circuit and Blocking Performance

Abstract :

High-power semiconductor switches play a vital role in applications ranging from electric vehicles and HVDC systems to defence technologies such as electric weaponry, submarines, combat vehicle drives, and avionics control systems. These switches must handle high current, withstand high voltages, and operate reliably under elevated temperatures. Silicon Carbide (SiC) devices offer significant advantages over their Silicon counterparts, including higher critical electric field strength and superior thermal conductivity. However, improving short-circuit and blocking performance remains a key reliability challenge that needs to be addressed. We enhanced the short-circuit performance of SiC VDMOSFETs by introducing a P+ implant near the p-base, which partially depletes the JFET region, lowering ISC and slowing heat build-up. A systematic optimization of implant parameters and a double-implant strategy increased the short-circuit withstand time, tSC from 2.74 μs to 19 μs with only a 12% rise in Ronsp. The design remains compatible with standard IGBT gate drivers, ensuring easy industrial adoption. Conventional FFR designs in SiC MOSFETs are prone to VBR degradation due to lithographic errors, dopant straggle, and negative oxide charge due to humidity, QH. To address this, we proposed a Mirrored Floating Field Ring (MFFR) structure, which improves tolerance to these variations. TCAD simulations for a 600 V device showed that MFFR reduces VBR degradation from 48% to 16%, enabling thinner drift layers and lower Ronsp while maintaining reliable breakdown performance.