| PhD Viva

Name of the Speaker: Mr. Chakravarti Bheemisetti (EE18D044)
Guide: Prof. Nagendra Krishnapura
Co-Guide: Dr. Saurabh Saxena
Online meeting link: https://meet.google.com/gbu-cnzq-fhi
Date/Time: 10th March 2025 (Monday), 3:30 PM
Title: Low-power SAR ADC Design Techniques for Time-Interleaved ADCs in High-speed Serial Link Receivers

Abstract :

Data center networking demands are growing rapidly due to cloud computing and workloads like machine learning and artificial intelligence, which need high data throughput. To meet these bandwidth needs, new electrical interfaces are being developed to achieve 224 Gb/s using PAM4 signaling. The main challenges for the serializer/deserializer (SERDES) receiver design include achieving high bandwidth and low noise for PAM4 signaling, providing sufficient gain and equalization for long channels. Additionally, power efficiency, area, and lane aspect ratio are crucial in designing SERDES channels in an SoC. To meet evolving standards, SERDES designs must have flexible equalization capabilities, often achieved through an ADC-based architecture, which shifts much of the equalization to the digital domain.

Due to this essential role, ADC circuits have been extensively studied over 40 years, and many problems associated with them have already been addressed. Recently, a new species of ADCs has appeared, and since then attracted lots of attention. These are ultra-high-speed (often exceeding 40 GS/s) ADCs of low or medium resolution (around 6 to 8 bit) built in CMOS processes. For a PAM4 224 Gb/s receiver, ADCs with sampling frequency of 112 GS/s are required. At such high sampling rate, massively time-interleaved (TI) successive-approximation (SAR) ADC architecture has emerged as the dominant choice due to its excellent power efficiency. However, the optimal interleaving configuration remains unclear, with state-of-the-art designs varying from simple conventional 1-rank interleaving to more complex 2-rank or even 3-rank hierarchical sampling. The best way to partition interleaving factors among different ranks has not yet been explored. Additionally, asynchronous SAR sub-ADCs are often utilized in these designs to push the sampling rate even further. This research investigates the design of high-speed SAR ADCs, focusing on circuit techniques that enhance timing complexity and conversion speed while maintaining low energy consumption. It also explores the limitations of single and dual-comparator asynchronous SAR ADCs, which have shown high power efficiency at higher conversion rates.

This work presents a 1.75-GS/s single channel 7-bit SAR ADC that is based on loop- unrolled architecture with N-comparators for N-bits. A memory-less fully asynchronous SAR is proposed to lower power consumption and reduce design complexity. A double-tail feed-backward (DTFB) dynamic comparator is proposed to meet the required speed and minimize thermal noise, which is a critical parameter for a 7-bit SAR ADC. The prototype ADC is implemented in a 3-nm CMOS process. The ADC achieves an SNDR/SFDR of 37/49 dB at Nyquist, 0.00055 mm2 area, and consumes 0.69 mW of power with 0.65 V, 0.9 V and 1.2 V supplies. The 1.2 V supply is used to generate SAR Vre f , 0.9 V is used for TH clocking, and 0.65 V is for the rest of the SAR core blocks. This leads to a best-in-class Walden figure of merit (FoMw) of 6.9 fJ/conv.-step and a Schreier FoM of 158 dB at Nyquist. This SAR ADC is used in a 64-way time-interleaved (TI) ADC to achieve 112 GS/s operation for use in an ADC-based 224 Gb/s PAM4 SERDES receiver.

The thesis also details the interleave circuit, clarifying that the SAR ADC was integrated within a larger receiver system rather than being taped out as an independent component. This integration required a method to accurately isolate and analyze the performance of a single SAR ADC. A novel de-embedding method was developed to overcome the complexities involved in separating the contributions of the interleaved architecture, ensuring measurement of the SAR’s standalone performance metrics.