| MS Seminar

Name of the Speaker: Ms. Meghna Misra (EE20S034)
Guide: Prof. Nagendra Krishnapura
Online meeting link: https://meet.google.com/yws-ejoa-fej
Date/Time: 3rd February 2025 (Monday), 4:00 PM
Title: Design of High Performance Crystal Oscillators for Frequency Synthesizers

Abstract :

KEYWORDS: Stable reference clock, crystal oscillator, low power, better phase noise, low complexity, lesser parasitics , better cost affectivity

The need of the current world of ever increasing data rate, and high speed seamless data transmission requires high efficiency and low noise clock sources for proper operation of multiple blocks in chips. For this purpose, a stable frequency source is much needed in communication and RF systems. The crystal oscillator plays an important role in supplying such a clean stable reference clock for various circuit building blocks such as phase-frequency locked loops, frequency synthesizers, memory elements. In this project, four 114 MHz crystal oscillators have been designed using 65 nm technology. The conventional Pierce Crystal Oscillator and differential crystal oscillator type architectures are used for the implementation of the same supporting both low voltage(1V) and high voltage(2.5V) supplies. We achieve a frequency tuning range of the oscillator as 7 kHz at TT(27 .C) when load capacitance is varied from 2 pF to 4.3 pF. The nominal case FOMs achieved with 7pFload at TT(27 .C) are 195.15 dB, 195.95 dB, 197.39 dB and 196.86 dB for the high voltage Pierce, low voltage Pierce, low voltage differential and high voltage differential crystal oscillators respectively. The nominal power consumption of these oscillators under the same conditions are 5.89 mW, 274 μW, and 1.321 mW and 8.335 mW respectively. The differential oscillator thus performs better than the conventional Pierce oscillator and appears to be a better choice for frequency references in phase-locked loops.