| Invited Talk

Name of the Speaker: Mr. Redwood EDA
Name of the Organizer: Prof. Nitin Chandrachoodan
Venue: ESB-244 (Seminar Hall)
Date/Time: 6th December 2024 (Friday), 10:00 AM
Title: Transaction-Level Verilog and its Ecosystem

Abstract :

Digital semiconductor design is at an inflection point where RTL-based design is no longer sufficient to support the industry. Several technologies show promise for the next generation, but none are the clear winner. This talk presents transaction-level design methodology and Transaction-Level Verilog which introduce higher-level modeling without sacrificing the ability to express RTL details. You'll see how TL-Verilog is used to create a flexible RISC-V CPU core generator, how it simplifies FPGA development, and how it is used in low-cost ASIC tapeouts.

Bring your laptop! Attendees will have the opportunity to code and simulate a small circuit from their browsers using the Makerchip IDE.

Speaker Bio:

Steve is the founder of Redwood EDA, a startup focused on next-generation digital circuit design and the democratization of semiconductor technologies. He is actively driving forward the Transaction-Level Verilog standard and provides the Makerchip online IDE for open-source semiconductor design. Formerly, as an engineer with DEC, Compaq, and Intel, Steve designed components for Alpha, Itanium, and x86 server CPUs and network architectures. Steve holds a BS in electrical engineering summa cum laude from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois.