| PhD Viva

Name of the Speaker: Mr. Vamshi Krishna (EE14D010)
Guide: Dr. Kamalesh Hatua
Online meeting link: https://meet.google.com/rgu-smuw-pfn
Date/Time: 7th October 2024 (Monday), 10:00 AM
Title: Investigation of cost effective techniques for fast switching and series-connection of SiC MOSFETs in the presence of significant layout parasitic inductance

Abstract :

SiC MOSFETs have emerged as the latest technology switching devices replacing Si-IGBTs in 600V to 1.7kV voltage range owing to their faster switching speeds and lower conduction losses. But, switching SiC MOSFETs at full speed is still a challenging task. They generate significant overshoot and ringing in the device voltages and currents. This is especially true when SiC MOSFETs are switched at full speed in a conventional layout design that is designed for Si-IGBTs. Special layout design techniques need to be used to minimize net parasitic layout inductance (Lp). Such layout techniques increase cost and complexity of the PCBs and thereby increase the net cost of the solution as well. The present work investigates various techniques to switch SiC MOSFETs in a fast and reliable manner in the presence of moderate Lp values. This lowers the cost and complexity of SiC MOSFET layout designs.

The first work proposes a low-cost, current-controlled analog active gate driver (AAGD) to limit the overshoot and ringing in the SiC MOSFET in the presence of moderate Lp values. This active gate driver uses a closed-loop di/dt controller to limit the device overshoots while Achieving the fast switching speed. Moreover, the di/dt controller is designed with freely available low-cost transistors. The performance of the designed AAGD is verified at various load currents and is found to be satisfactory, the proposed AAGD is able to save turn-off losses by 16% and turn-on switching losses by 23.7%.