| MS Seminar

Name of the Speaker: Mr. Nagabhushana Rao(EE21S039)
Guide: Prof. Shanthi Pavan
Venue: ESB-244 (Seminar Hall)
Online meeting link: meet.google.com/ctf-xzba-mds
Date/Time: 21st August 2024 (Wednesday), 5:00 PM
Title: Design of a Low-power Time-Interleaved SAR ADC for the Backend of a Continuous Time Pipelined ADC Abstract:

Abstract :

This work focuses on the design of a low-power Successive Approximation Register Analog-to-Digital Converter(SAR-ADC) that uses a monotonic capacitor switching procedure to reduce the average switching energy and total capacitance compared to converters that use the conventional method. In this switching procedure, the input common-mode voltage gradually converges to the ground. For better linearity, we used a bootstrap switch. This switching scheme requires top-plate sampling, so it is prone to top-plate parasitics. We introduce a custom-designed sandwich capacitor to address parasitics associated with the top plate and leverage segmentation to lower the required capacitance further. Careful attention is given to ratio matching between capacitor components (C, Cc) to ensure accuracy with random variations. Additionally, splitting the Most Significant Bit (MSB) capacitors mitigates common-mode variations. The design incorporates relaxed specifications for comparator noise due to the front-end gain provided by Continuous time pipelined ADC (CTP), resulting in a low-area comparator since the dynamic range of the SAR-ADC in the CTP is only half of the full scale, reducing the impact of absolute offset. Finally, the implementation features simple digital logic for asynchronous, self-timed SAR control, streamlining the overall design and enhancing efficiency.