| PhD Seminar

Name of the Speaker: Mr. Rajarshi Basu (EE19D412)
Guide: Prof. Mahesh Kumar
Venue: ESB-244 (Seminar Hall)
Online meeting link: https://meet.google.com/qmd-dfkc-wak
Date/Time: 20th August 2024 (Tuesday), 4:00 PM
Title: Developing a Loss Minimization Algorithm for the 3-port Converter in a Microgrid Structure

Abstract :

The onset of microgrids has reconfigured the power system, enabling the integration of various distributed energy resources and decentralizing power generation across the electrical grid. To facilitate this, numerous multiport converter topologies with a reduced number of components have been proposed in the literature. One such multiport topology, the 3-port converter, has been proposed in a prior work of the authors. This converter minimizes the number of switches while integrating different distributed energy resources, resulting in increased current flows in some of the devices, which increases the losses in the system. To address this challenge, this work develops a loss minimization algorithm for the 3-port converter topology in a real-time environment. The proposed algorithm derives an analytical expression for power loss considering different power loss components and only two control variables, which facilitates easier implementation in a real-time environment. The obtained power loss function is minimized using a simple gradient-descent-based deterministic optimization approach. To reduce the computational burden in the optimization process, a graphical analysis is done, which assists in choosing appropriate input parameters. Further, to implement the optimized results, a novel port current angle adjustment strategy is proposed that embeds the results of the optimization process into the microgrid control by adjusting the dq0 voltage angles. To validate the proposed algorithm and implementation strategy, a microgrid structure with multiple subgrids built using the 3-port converter is considered for testing. The entire analysis is verified for a 5 kW converter with 110 V (rms) AC side voltage by performing Controller Hardware in Loop (C-HIL) operation using OPAL-RT OP4510 HIL simulator.