| PhD Seminar

Name of the Speaker: Mr. Ajit Kumar Upadhiya (EE20D750)
Guide: Prof. Lakshminarasamma
Co-Guide: Prof. Mahesh Kumar
Venue: ESB-244 (Seminar Hall)
Date/Time: 20th August 2024 (Tuesday), 3:00 PM
Title: Design of Switched-Capacitor Based Multilevel Inverter for Renewable Energy Application

Abstract :

Transformerless inverters are a popular choice in Photovoltaic (PV) generation systems because of their cost-effectiveness and highly efficient operation. Nonetheless, challenges associated with common-mode voltage have motivated the exploration of alternative topologies, control methodologies, and modulation strategies. In common-ground type inverters, the load and source ground terminals are interconnected, resulting in the bypassing of parasitic capacitances and the complete elimination of leakage current. This work proposes a novel eleven-level switched-capacitor based inverter topology featuring a common ground connection between the source and load. This topology can achieve a five-fold voltage gain, making it well suited for low-voltage PV systems. The common-ground (CG) feature of this inverter effectively eliminates leakage current and significantly reduces electromagnetic interference (EMI) by bypassing stray capacitance. Consequently, there is no need for an EMI filter. The voltage balancing of the capacitors occurs automatically, without the need for any control scheme, sensors, or closed-loop controllers. A detailed comparison with established CG-based topologies is carried out, emphasizing the parameters of component count, total standing voltage, cost, and volume, which clearly indicate the inverter’s improved attributes. The pulse width modulation (PWM) scheme, design guidelines for the switched-capacitor (SC), and loss analysis, including thermal modeling, are discussed in detail. The proposed inverter’s feasibility and performance are verified through detailed simulation and experimental studies.