| Invited Talk

Name of the Speaker: Dr. SAION K. ROY
Name of the Organizer: Prof. Janakiraman Viraraghavan
Venue: ESB-244 (Seminar Hall)
Date/Time: 19th August 2024 (Monday), 2:00 PM
Title: Energy-accuracy trade-offs of resistive in-memory computing architectures.

Abstract :

Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. To understand this trend, we propose using the signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters that affect it. Our analysis focuses on the fundamental limits on the compute SNDR of MRAM, ReRAM, and FeFET-based IMCs, employing parameter variation and noise models validated against measured results from a recent MRAM-based IMC prototype in a 22nm process. At high output signal magnitude, we find that the maximum achievable SNDR is limited by the pre-ADC array non-idealities such as the conductance variations, parasitic resistances, and current mirror mismatch, whereas the ADC thermal noise limits the SNDR at small signal magnitudes. Furthermore, the increase in conductance contrast enhances the maximum achievable SNDR only until it reaches a value of approximately 12. Among the evaluated eNVM technologies, ReRAMs and FeFETs exhibit high energy efficiencies and high SNDR, as their low conductance values result in lower currents and reduces the impact of wire parasitics. In all cases, across all three device types, DP dimension, ADC precision, and conductance contrast, the maximum achievable SNDR is found to be in the range of 18dB-22dB, barely meeting the minimum needed for achieving an inference accuracy close to an equivalent fixed-point digital architecture. Finally, we demonstrate a network-level accuracy of 84.5% when mapping a ResNet-20 (CIFAR-10) by ReRAM-based architecture at an SNDR of 22dB, which MRAM and FeFET-based architectures cannot realize. This result clearly implies the need for other approaches, e.g., algorithmic and learning-based methods, to improve the inference accuracy of resistive IMC architectures. Additionally, this talk will briefly introduce the security vulnerabilities of resistive IMCs that arise due to their low compute SNDR.

Speaker Bio:

SAION K. ROY (Student Member, IEEE) received his Ph.D. from the University of Illinois at Urbana–Champaign, USA, in 2024, and his B.Tech. and M.Tech. degrees from the Indian Institute of Technology Kharagpur, India, in 2018. His research interests encompass energy-efficient integrated circuit design and analysis, with a focus on eNVM-based in-memory computing architectures for machine learning (ML) algorithms. He is currently an incoming postdoctoral researcher at Northeastern University, where he will be concentrating on the security vulnerabilities of ML accelerators. His Ph.D. research resulted in publications in venues such as ESSCIRC, CICC, IEDM, ICCAD, JSSC, and JxCDC. He has also been a reviewer for JETCAS, TVLSI, and JSSC.