| MS TSA Meeting

Name of the Speaker: Mr. Sagnik Basu (EE20S016)
Guide: Prof. Shreepad Karmalkar
Online meeting link: https://meet.google.com/icx-rzdv-xsj
Date/Time: 1st August 2024 (Thursday), 9:00 AM
Title: Exploring Device Level Insights to Enhance the Performance of RF-SOI Switches

Abstract :

n today’s wireless communication system, Radio Frequency (RF) switches are one of the key building blocks used in an RF front-end module (FEM). For better-integrating capability and better performance CMOS Silicon-On-Insulator (SOI) technology has emerged over the past few years as the dominant technology for RF switches due to its significantly lower parasitic capacitance, higher power handling capability and better linearity. The influence of device parameters and device phenomena on RF-SPST (Single Pole Single Throw) switch figure of merits (FOM) and the trade-offs among these parameters to achieve better performance have been presented through simulation in 130 nm SOI technology. The impact of body potential on RF switch FOMs and the floating body phenomena observed in body-contacted FETs (specially for devices having T-body contact and larger finger width (wf)) used in RF switch stack has been briefly analyzed through simulation. The appropriate choice of wf and number of fingers (nf) for achieving good small signal and large signal performance by minimizing the floating body effect have been analyzed.

The conventional gate and body floating resistive biasing technique and stacking of transistors used in RF switches is not suitable for larger power handling capability (Pmax). New resistive biasing techniques namely 1st bias scheme and 2nd bias scheme have been proposed to achieve higher Pmax and better OFF state linearity. The simulation results demonstrate that the Pmax improves by 5 dBm and 5.25 dBm in 1st scheme and 2nd scheme respectively as compared to the conventional biasing for a 1 mm, 18 stack shunt SPST switch in OFF state. There is almost 25 dBm and 20 dBm improvement in H2 and 6 dBm and 4 dBm improvement in H3 at Pin of 35 dBm and fin of 890 MHz for 1st scheme and 2nd scheme respectively, as compared to the conventional biasing.