| MS TSA Meeting

Name of the Speaker: Mr. ABHISHEK KUMAR (EE20S138)
Guide: Nagendra Krishnapura
Venue: Online
Online meeting link: https://meet.google.com/okk-cpuj-rca?authuser=0&hs=122
Date/Time: July 8th 2024 (Monday), at 12:00PM to 1.00PM
Title: Jitter and Spurious Tone Reduction in Sub-Sampling Phase-Locked Loops with Switched-Transconductor and Switched-Capacitor Loop Filters

Abstract :

The area of sub-sampling phase-locked loops(PLLs) with large multiplication factors can be significantly reduced using a polarity-switched transconductor and a switched-capacitor loop filter. The transconductor’s output current polarity has to be switched in a small fraction of the reference cycle. The duration spent in each polarity determines one of the critical parameters of the loop gain and influences stability. Because the transconductance value required is small, fast switching is challenging. This difficulty is compounded by the high DC gain requirement, which forces the use of gain-boosting cascodes. Realizing the transconductor using small bias currents results in slow switching. High bias currents for faster switching and reducing the transconductance by attenuation or partial cancellation significantly increase the excess noise factor. This work proposes a topology for the gain-boosting opamp that improves the switching time while reducing the excess noise factor. The phase noise contribution of the transconductor in a sub-sampling PLL is inversely proportional to the phase detector gain. The phase detector gain decreases with a shift in the zero crossings of the driving waveform and feedthrough in the sampling switches. This work modifies the layout of the sampling switches to reduce the feedthrough and the driving circuit to maintain the operating point within tighter bounds. A prototype PLL ranging from 24.6 GHz to 29 GHz with a 50 MHz reference clock and 1.5 MHz bandwidth in the CMOS 65 nm LP process uses a loop-filter capacitor of 6 pF. The measured phase noise is -97 to -100 dBc/Hz at 500 kHz offset and -118 to -120 dBc/Hz at 10 MHz offset. The integrated jitter is 230-240 fs. The power consumption varies from 23 to 25 mW, demonstrating a FoM of around 239 dB. The sub-sampling PLL occupies an active area of 0.136 mm2.