| Invited Talk

Name of the Speaker: Dr. Gurtej S Sandhu
Venue: ESB-244 (Seminar Hall)
Date/Time: 15th April 2024 (Monday), 12:00 PM
Title: The Future of Memory Chip technology and role of innovation

Abstract

A commitment to innovation and creativity at a system level is required to meet demands of this data age. These innovations will help fuel the next generation of capabilities in generative artificial intelligence (GenAI) and enable technologies such as self-driving cars, smart medicine, industrial automation, space exploration etc. which sounded like science fiction not so long ago. Several new memory technologies have been proposed over the years with no clear winners. Some of the critical factors which need to be considered for a successful implementation of a new technology include why and when alternate memory technologies may be needed, what are the performance criteria and related requirements, and what needs to happen in the ecosystem to support a successful market deployment of new technology. Chip complexity has been increasing exponentially so semiconductor manufacturing has become more and more reliant on advanced modeling tools to help engineers make informed decisions for building process flows faster, with less empirical experimentation. Traditional modeling innovation however, has not kept up to meet the challenges of developing future chips at the pace and efficiency required for practical solutions. A successful solution will require holistic approach across all vectors in the chip ecosystem and multi-disciplinary collaboration across the entire framework of chip building disciplines: structure and materials, unit process/metrology and manufacturing tools modeling across wafer processing in fab, and packaging in assembly. These solutions must be domain and application focused and will require new breakthroughs in data processing and computational capabilities to enable more efficient and powerful multiscale modeling using advanced AI and physics-based approaches.

Biography:
Gurtej Sandhu is Principal Fellow and Corporate Vice President at Micron Technology. In his current role, he is responsible for Micron’s end-to-end (Si-to-Package) R&D technology roadmaps. The scope includes driving and managing the Modeling engineering organization to resource and execute on developing innovative technology solutions for future memory scaling. Dr. Sandhu’s responsibilities include managing interactions with research consortia around the world. He has been actively involved with a broad range of process technologies for IC processing and has pioneered several process technologies currently employed in mainstream semiconductor chip manufacturing. Dr. Sandhu received a degree in electrical engineering at the Indian Institute of Technology, New Delhi, and a Ph.D. in physics at the University of North Carolina, Chapel Hill, in 1990. He is recognized as one of the top inventors in the world. In 2018, he received the IEEE Andrew S. Grove Award for outstanding contributions to silicon CMOS process technology for chip scaling.