| PhD Seminar

Name of the Speaker: Mr. Chakravarti Bheemisetti (EE18D044)
Guide: Prof. Nagendra Krishnapura
Co-Guide: Dr. Saurabh Saxena
Venue: ESB-210B (Conference Hall)
Date/Time: 18th March 2024 (Monday), 11:00 AM
Title: Low-power SAR ADC design techniques for time-interleaved ADCs in high-speed serial link receivers.

Abstract

The talk will present a 1.75-GS/s single channel 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) for a 224-Gbps SERDES. This SAR ADC is based on loop-unrolled (LU) architecture with N-comparators for N-bits. A timing-free, truly asynchronous-ready clock logic is proposed to lower the power consumption and reduce design complexity. A double-tail feed-backward (DTFB) dynamic comparator is proposed to meet the speed and reduce thermal noise which is a critical parameter for a 7-bit SAR ADC. The prototype ADC is implemented for the first time 3nm-CMOS to achieve an SNDR/SFDR of 37/49 dB at Nyquist, at 1.75-GS/s with an area of 0.00055 mm2 and consumes 0.69 mW leading to a best-in-class Walden figure-of-merit (FoMw) of 6.9 fJ/conv.-step and a Schreier FoM of 158 dB at Nyquist. This SAR ADC is used in a 64-way time-interleaved (TI) ADC to get 112GS/s speed for an ADC-based 224Gb/s PAM4 SERDES receiver.