| MS Seminar

Name of the Speaker: Mr. GOROJU RAJASHEKAR (EE15S021)
Guide: Prof. Nagendra Krishnapura
Online meeting link: https://meet.google.com/upp-scgq-pam?authuser=0&hs=122
Date/Time: 29th January 2024 (Monday), 11:15 AM
Title: An Active-RC Filter Based On Chip Sinusoidal Oscillator for Testing High Linearity Devices.

Abstract

ADCs with a resolution of 18-bit or higher require a low-distortion sinusoidal source for testing. Bench-top equipment capable of generating a sinusoidal signal of -140dBc is available. Lately, Chip-based solutions are finding importance as they give an advantage in portability. It can be integrated with the device under test on the same board, so it is possible to demonstrate the DUT performance in an environment where a large test setup cannot be arranged.

In this work, a low distortion oscillator that is useful for testing high-resolution ADCs is demonstrated in a 0.6 um CMOS process. On-chip oscillators at low frequencies use active RC or gm.C architectures. For obtaining a stable sinusoidal waveform, an amplitude stabilization loop is necessary. An Active-RC filter wherein every node is a virtual ground or opamp output is used

to build an oscillator core. A peak detector is used to sense the amplitude of the oscillator and adjust the oscillator core loop gain to unity. Apart from the filter used in the oscillator core, modulation of the oscillator’s loss due to ripple in the output of the amplitude stabilization loop required for stable sinusoidal oscillations is a significant contributor to distortion. A four-phase full-wave rectifier used as a peak detector, combined with second-order ripple filtering, minimizes this effect. The oscillator prototype can generate 1 or 10 kHz and has THD < -115 dBc while driving 8 Vppd output. The oscillator occupies 8.5mm2 and consumes 50 mW from 5 V. Measured frequency and amplitude stability over 166 min are 0.95 mHz (17.3 mHz) and 91 uV (45 uV) at 1 kHz (10 kHz).