| PhD Viva

Name of the Speaker: Mr. Pavan CH L N (EE13D038)
Guide: Prof. Deleep R Nair
Online meeting link: https://meet.google.com/tcf-zkgr-tzi
Date/Time: 11th January 2024 (Thursday), 4:30 PM
Title: Characterization and analysis of Random Telegraph Noise in SiGe channel HKMG PMOSFETs.

Abstract

The never-ending quest for higher performance, low power dissipation and more functionality per integrated circuit resulted in aggressive scaling of MOSFETs. Innovation in the semiconductor industry has been driving the CMOS device scaling and thereby resulting in continued transistor performance improvement. Device scaling has resulted in an increase of electric fields in the device, increase in operating temperatures of the chip, thereby increasing reliability concerns. Further, introduction of new materials, processes and device architectures have also contributed to increased reliability challenges.

One of the recent reliability concerns of scaled MOS transistors is random telegraph noise (RTN). It is the fluctuation in drain current of a MOSFET caused by random trapping and detrapping of channel carriers into discrete traps at the semiconductor-oxide interface or in the gate insulator. It results in performance fluctuation, characterized by fluctuation in threshold voltage (∆VT). RTN becomes important for scaled devices as its impact increases with device scaling.

Silicon-Germanium (SiGe) has been identified as an alternate channel material to Silicon to obtain lower threshold voltage and higher mobility in pMOS transistors. It is the only FET channel material other than silicon in commercial high volume production. There has been a revival of interest in Silicon-Germanium in the recent years as potential channel material for mobility improvement at lower nodes.

This thesis is focused on investigation of impact of RTN in SiGe channel HKMG PMOSFETs from IBM’s 32nm low power process technology node. The devices used in this work do not have a Si-cap layer between semiconductor and gate stack. This represents a true high-mobility channel and the gate stack interface. The work in this thesis involves extensive characterization of RTN, implementation of a variety of tools and algorithms for RTN data analysis. Further, a detailed study of RTN traps causing two-level RTN is carried out to understand the trap behavior and its impact on device electrostatics. The impact of RTN trap on device performance is evaluated in terms of relative RTN magnitude and RTN-induced ∆VT. Further, statistical investigation of RTN is carried out in which statistical estimates of trap number and single trap RTN-induced ∆VT are extracted. This helps to quantify the reliability constraints set by RTN which in turn helps to get a better understanding of device and circuit interaction for a robust circuit design.

Our results show that a comparison of impact of RTN between 32nm node SiGe channel PFETs used in this work and 28nm node RMG planar Si-channel PFETs with comparable Tinv, that the impact of RTN in the inversion region is similar for SiGe and Si channel devices.