Abstract: Synthesizing standard cell layouts is challenging in advanced technology nodes due to dense, complex design rules, which also make manual layout generation time-consuming. This work automates the generation of standard cell layouts with optimal area and wirelength. Given a netlist of transistor instances with their dimensions, nets, and input/output pins, layout generation involves transistor placement, net routing, and pin assignment. Algorithms for standard cell generation range from exact methods such as Satisfiability Modulo Theories (SMT) to inexact machine learning approaches. Placement assigns locations to front-end-of-line (FEOL) structures forming pFETs and nFETs, with transistors placed along two horizontal axes for the pull-up and pull-down networks. Here, placement is formulated as a constrained optimization problem using the CP-SAT solver, which combines Constraint Programming with Boolean SATisfiability, to find the transistor permutation that minimizes cell width. Routing uses local interconnect and the first two metal layers, formulated in CP-SAT as a min-cost network flow problem over a three-dimensional grid, with total metal length as a proxy for parasitics and the objective of minimization. Evaluation on a predictive 7nm FinFET (ASAP7) PDK shows the method generates optimal placements comparable to reference layouts, with lower runtimes than prior approaches.

Event Details
Title: Standard Cell Layout Synthesis using Constraint Programming with SATisfiability methods
Date: September 30, 2026 at 03:30 PM
Venue: ESB 234 (Malaviya Hall)
Speaker: Mr. Harish Madhavan (EE23S017)
Guide: Dr S Ramprasath
Type: MS seminar

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