Course Details

Course details of EE6332
Course NoEE6332
Course TitleModeling and Optimization in VLSI
Course ContentThe current version of the course will focus on the following problems:- 1. Review of Level-1 SPICE model - Definition of Idlin, Idsat, Vtlin and Vtsat 2. Introduction to process variations 3. Statistical Compact Model Extraction (SCME) - Problem Formulation 4. Forward and Back propagation of variance. 5. Linear and Quadratic Back Propagation of variance. 6. Modeling Ioff and Non-linear optimization 7. Review of RC model of gate delay 8. Logical effort model for delay 9. Path delay optimization - Capacitance as variables 10. Buffering 11. Path delay optimization - Gate size as variables 12. Static Timing Analysis (STA) 13. Timing slack propagation 14. STA inspired node based gate sizing formulation 15. Introduction to Geometric Programs (GP) 16. Example GP problems and solutions 17. Gate sizing as a GP 18. Circuit timing wall 19. Alternate formulations including minimum area and power. 20. The continuous solution and convexity 21. Discretizing the continuous solution 22. Gate downsizing based on available slack 23. Introduction to Statistical Static Timing Analysis 24. Machine Learning in design optimization 25. Data preparation and curation 26. Simple Regression Models 27. Model building and application to physical design 28. Reinforcement learning
Course Offered this semesterNo
Faculty Name