Saurabh Saxena


Assistant Professor

Department of Electrical Engineering
Indian Institute of Technology Madras

Room 245A, Electrical Sciences Block
Chennai, TN 600036

Phone: +91-44-22574457


I am interested in exploring system and circuit level techniques aimed at enhancing speed and reducing power consumption in information gathering, processing, and communicating, in both wireless and wireline systems. Wireline communication includes data transfer to and from processors, hierarchial memory storage, and source/destination of information. Transmitting ideal signals for data bits, equalizing for frequency dependent channel loss, recovering sampling clock on receiver side, and recovering error-free data are some of the critical operations in wired communication. Lowering the power consumption for roughly error-free high speed data transfer is one of the goals of my research.

Low jitter and low power high speed clock generation is critical for both wireless and wireline communication. Multiple frequency synthesizers with few-to-subpicosecond clock jitter are used in standalone integrated systems. Designing a compact and an energy efficient frequency sythesizer with low jitter is one of my research projects.

Low power sensor interface circuits, ultra-low power radio for wireless sensor network, software-defined radio for multiple wireless standards, and board-level high data rate wireless interconnect are some of the wireless communication links which interest me.