Assistant Professor
Department of Electrical Engineering
Indian Institute of Technology Madras,
Chennai 600036

Email: ravia@ee.iitm.ernet.in
Phone: +91-44- 2257 8410

Courses Taught
EE 628 - CAD of Digital ICs (Jan-April 2004)
EE 540 - Digital IC Design (August-November 2004)

Research Interests

Computer-Aided Design Methods for VLSI, Signal integrity in digital VLSI, Interconnect Analysis, Timing analysis and modeling, Low power design, VLSI Testing.

Education

Ph.d(2000), M.S(1998) in Electrical and Computer Engineering - Carnegie Mellon University, Pittsburgh, PA, USA
B.Tech(1996) in Electrical and Electronics Engineering - Indian Institute of Technology, Madras

Work Experience

Advisory Software Engineer - IBM Electronic Design Automation, Austin (Jan.2001-Mar.2003)

Honours

Awarded the IBM co-operative fellowship for three consecutive years (1997-98,1998-99,1999-2000)
(Here is the 1999 announcement)

Publications

1) Aniket Singh and Ravishankar Arunachalam,"A Novel Algorithm for Testing Crosstalk-induced Delay Faults in VLSI Circuits," International Conference on VLSI Design,Kolkata, 2005

2) Siddharth Garg, Siddarth Tata and Ravishankar Arunachalam,"Static transition probability analysis under uncertainty," IEEE International Conference on Computer Design, San Jose, 2004

3) Aniket Singh and Ravishankar Arunachalam,"Maximization of Aggressor Influence in Crosstalk-Delay Testing," Proceedings of the 8th VLSI Design and Test Workshops, Mysore, 2004

4) Siddharth Tata, Siddharth Garg and Ravishankar Arunachalam,"Gate Level Dynamic Power Estimation in the Presence of Varying Process Parameters," Proceedings of the 8th VLSI Design and Test Workshops, Mysore, 2004

5) Ravishankar Arunachalam, Emrah Acar and Sani Nassif, "Optimal Shielding/Spacing metrics for Low-Power Design," IEEE Annual Symposium on VLSI, Feb.2003

6) Emrah Acar, Ravishankar Arunachalam and Sani Nassif, "Predicting short-circuit power using timing models," Asia-Pacific Design Automation Conference, Japan, Jan.2003

7) Ravishankar Arunachalam, Ronald D. Blanton and Lawrence Pileggi, "Accurate coupling-centric timing analysis incorporating temporal and functional isolation," VLSI Design Journal, November 2002

8) Ravishankar Arunachalam, Emrah Acar and Sani Nassif, "Evaluation Method and metrics of shielding/spacing approaches for coupling avoidance,"IBM Research Report,2002

9) Ravishankar Arunachalam, Ronald D. Blanton and L.T.Pileggi, "False Coupling Interactions in Static Timing Analysis," Design Automation Conference, June 2001

10) Ravishankar Arunachalam and Lawrence Pileggi, "Timing Closure in DSM Design," Integrated System Design Magazine, September 2000

11) Ravishankar Arunachalam, Karthik Rajagopal and Lawrence Pileggi, "TACO: Timing Analysis With Coupling," Design Automation Conference, June 2000

12) Paul D.Gross, Ravishankar Arunachalam, Karthik Rajagopal and Lawrence Pileggi, "Determination of Worst-case Aggressor Alignment for Delay Calculation," IEEE International Conference on Computer-Aided Design, Nov. 1998

13)Ravishankar Arunachalam, Florin Dartu and Lawrence Pileggi, "CMOS Gate Delay Models for General RLC Loading," International Conference on Computer Design, October 1997

Patents

US Patent Number 6,651,229 "Generation of Refined Switching Windows in Static Timing Analysis," 2001 (co-inventors David Hathaway and Robert Allen, I.B.M Corporation)