I work on various aspects of digital system design, mostly in the context of signal processing.
A complete list of my publications is available.
The most recent ones are listed below:
- Kim, Y., Venkataramani, S., Chandrachoodan, N., and Raghunathan, A. 2019. Data Subsetting: A Data-Centric Approach to Approximate Computing. Proceedings of Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, 576–581.
- Bathla, S., Rao, R.M., and Chandrachoodan, N. 2019. A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, 2, 376–386.
- Mitra, G., Vairam, P.K., SLPSK, P., Chandrachoodan, N., and Veezhinathan, K. 2019. White Mirror: Leaking Sensitive Information from Interactive Netflix Movies using Encrypted Traffic Analysis. CoRR abs/1903.06475.
- Natarajan, K. and Chandrachoodan, N. 2018. Lossless Parallel Implementation of a Turbo Decoder on GPU. Proceedings - 25th IEEE International Conference on High Performance Computing, HiPC 2018, 133–142.
- Gokulkrishnan, V., Kamakoti, V., Chandrachoodan, N., and Potluri, S. 2018. A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, 1–4.
- Celia, D., Vasudevan, V., and Chandrachoodan, N. 2018. Optimizing power-accuracy trade-off in approximate adders. Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018, 1488–1491.
- Celia, D., Vasudevan, V., and Chandrachoodan, N. 2018. Probabilistic Error Modeling for Two-part Segmented Approximate Adders. Proceedings - IEEE International Symposium on Circuits and Systems.
- Geetha, A., Mekala, N., Chandrachoodan, N., Mishra, A., Prabhakar, A., and Bhattacharya, S. 2017. Design of a spectrometer for frequency domain optical coherence tomography working at 1325 nm. Optics InfoBase Conference Papers.
- Rangachari, S., Balakrishnan, J., and Chandrachoodan, N. 2017. Scenario-Aware Dynamic Power Reduction Using Bias Addition. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, 2, 450–461.
- Celia, D. and Chandrachoodan, N. 2016. Guided multilevel approximation of less significant bits for power reduction. 2016 20th International Symposium on VLSI Design and Test, VDAT 2016.