- Chembiyan Thambidurai and Nagendra Krishnapura, "On Pulse Position Modulation and its Application to PLLs for Spur Reduction," IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 58, no. 7, pp. 1483-1496, July 2011. (paper)
- Nagendra Krishnapura, Abhishek Agrawal, and Sameer Singh, "A High IIP3 Third Order Elliptic Filter with Current Efficient Feedforward Compensated Opamps," IEEE Transactions on Circuits and Systems II-Express Briefs, vol. 58, no. 4, pp. 205-209, April 2011. (paper)
- Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, "Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time ΔΣ Modulators," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 9, pp. 676-680, Sep. 2010. (paper)
- S. Pavan, N. Krishnapura, R. Pandarinathan, P. Sankar, "A Power Optimized Continuous-time Delta-Sigma Modulator for Audio Applications," IEEE Journal of Solid State Circuits, vol. 43, no. 2, pp. 351-360, Feb. 2008. (paper)
- S. Pavan and N. Krishnapura, "Automatic Tuning of Time Constants in Continuous-Time Delta Sigma Modulators," IEEE Transactions on Circuits and Systems-II: Express Briefs, pp. 308-311, Apr. 2007.(paper)
- N. Krishnapura and Y. Tsividis, "Micropower low-voltage analog filter in a digital CMOS process," IEEE Journal of Solid State Circuits, vol. 38, no. 6, pp. 1063-1067, Jun. 2003. (paper)
- Y. Tsividis, N. Krishnapura, Y. Palaskas, L. Toth, "Internally varying analog circuits minimize power dissipation" IEEE Circuits and Devices Magazine, vol. 19, no. 1, pp. 63-72, Jan. 2003. (paper)
- N. Krishnapura and Y. Tsividis, "Noise and Power Reduction in Filters Through the Use of Adjustable Biasing," IEEE Journal of Solid State Circuits, vol. 36, no. 12, pp. 1912-1920, Dec. 2001. (paper)
- D. Frey, Y. Tsividis, G. Efthivoulidis, and N. Krishnapura, "Syllabic-companding Log Domain Filters," IEEE Transactions on Circuits and Systems II, vol 48, no. 4, pp. 329-339, Apr. 2001.(paper)
- N. Krishnapura, Y. Tsividis, and D. R. Frey, "Simplified Technique for Syllabic Companding in Log-domain Filters," Electronics Letters, vol. 36, no. 15, pp. 1257-1259, 20th Jul. 2000.(paper)
- N. Krishnapura and P. Kinget, "A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS," IEEE Journal of Solid State Circuits, vol. 35, no. 7, pp. 1019-1024, Jul. 2000. (paper)
- L. Toth, Y. Tsividis, and N. Krishnapura, "On the Analysis of Noise and Interference in Instantaneously Companding Signal Processors," IEEE Transactions on Circuits and systems-II, vol. 45, no. 9, pp. 1242-1249, Sep. 1998. (paper)
Journal papers
Conference papers
- Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, and Debasish Behera, "A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay," Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, September 2011. (paper, slides)
- Nagendra Krishnapura, "Electronic Time Stretching for Fast Digitization," 2011 International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 15-18 May 2011.
- Nagendra Krishnapura, "Efficient Determination of Feedback DAC Errors for Digital Correction in Delta-Sigma A/D Converters," 2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, 31 May-2 Jun. 2010. (paper, slides)
- Shankar Parameswaran and Nagendra Krishnapura, "A 100µW Decimator for a 16 Bit 24kHz Bandwidth Audio ΔΣ Modulator," 2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, 31 May-2 Jun. 2010. (paper, slides)
- Chembiyan Thambidurai and Nagendra Krishnapura, "Spur Reduction in Wideband PLLs by Random Positioning of Charge Pump Pulses," 2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, 31 May-2 Jun. 2010. (paper, slides)
- Nagendra Krishnapura, Varun Gupta, Neetin Agrawal, "Compact Lowpass Ladder Filters Using Tapped Coils," 2009 International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009. (paper, slides)
- Leburu Manojkumar, Arun Mohan, Nagendra Krishnapura, "A Comparison of Approaches to Carrier Generation in Zigbee Transceivers," 22nd International Conference on VLSI Design, New Delhi, India, 5-9 Jan 2009.(paper, slides)
- N. Krishnapura and S. Pavan, "Negative Feedback System and Circuit Design," Full Day Tutorial at the 22nd International Conference on VLSI Design, 5-9 January 2009, New Delhi, India. (Lecture and notes)
- N. Krishnapura and S. Pavan, "Oversampling Analog to Digital Converters," Full Day Tutorial at the 21st International Conference on VLSI Design, 4-8 January 2008, Hyderabad, India. (Lecture and notes)
- S. Pavan, N. Krishnapura, R. Pandarinathan, P. Sankar, "A 90 microwatt 15 bit continuous-time delta-sigma ADC for digital audio," 33rd European Solid State Circuits conference, pp. 198-201, Sep. 2007, Munich, Germany. (paper)
- N. Krishnapura, M. Barazande-Pour, Q. Chaudhry, J. Khoury, K. Lakshmikumar, A. Aggarwal, "A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission," IEEE International Solid State Circuits Conference, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.(paper, slides)
- N. Krishnapura and Y. Tsividis, "A Micropower Log-Domain Filter Using Enhanced Lateral PNPs in a 0.25um CMOS Process," 2001 VLSI Symposium on Circuits , pp. 179-182, Jun. 16 2001, Kyoto, Japan.(paper, slides)
- N. Krishnapura and Y. Tsividis, "Dynamically Biased 1MHz Low-pass Filter with 61dB peak SNR and 112dB Input Range," IEEE International Solid State Circuits Conference, pp. 360-361,465, slide supplement pp. 292-293,507, Feb. 4-7 2001, San Fransisco, USA.(paper, slides)
- N. Krishnapura and P. Kinget, "A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS," European Solid State Circuits Conference, pp. 144-147, Sep 21-23 1999, Duisburg, Germany. (paper, slides)
- N. Krishnapura, S. Pavan, C. Mathiazhagan, and B. Ramamurthi, "A Baseband Pulse Shaping Method for Gaussian Minimum Shift Keying," IEEE International Symposium on Circuits and Systems, vol. 1, pp. 249-252, Jun 1-3 1998, Monterey, California. (paper, slides)
- N. Krishnapura, Y. Tsividis, K. Nagaraj, and K. Suyama, "Switched Capacitor Companding Filters," IEEE International Symposium on Circuits and Systems, vol. 1, pp. 480-483, Jun 1-3 1998, Monterey, California. (paper, slides)
- L. Toth, Y. Tsividis, and N. Krishnapura, "Analysis of Noise and Interference in Companding Signal Processors," IEEE International Symposium on Circuits and Systems, vol. 1, pp. 143-146, Jun 1-3 1998, Monterey, California. (paper, slides)
Patents
- I. Shpantzer, M. Tseytlin, Y. Achiam, A. Salamon, I. Smilanski, O. Ritterbush, P. S. Cho, L. Guoliang, J. Khurgin, Y. Meiman, A. Demir, P. Feldmann, P. Kinget, N. Krishnapura, J. Roychowdhury, J. Schwarzwalder, C. Sciabarra, "System and method for code division multiplexed optical communication," US 7,167,651, Jan. 23, 2007.
- I. Shpantzer, Y. Meiman, M. Tseytlin, O. Ritterbush, A. Salamon, P. Feldmann, A. Demir, P. Kinget, N. Krishnapura, J. Roychowdhury, "System and method for orthogonal frequency division multiplexed optical communication," US 7,076,169, Jul. 11, 2006.
- N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing," US 6,816,003, Nov. 9, 2004.
- N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing," US 6,717,461, Apr. 6, 2004.
- N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing," US 6,683,492, Jan. 27, 2004.
- P. Kinget and N. Krishnapura, "Glitch Free Phase Switching Synthesizer," US 6,671,341, Dec. 30, 2003.
- P. Kinget and N. Krishnapura, "Programmable Frequency Divider," US 6,281,721, Aug. 28, 2001.