TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 0.27/0.18 Vth 0.50 -0.50 volts SHORT 20.0/0.18 Idss 549 -267 uA/um Vth 0.51 -0.51 volts Vpt 4.7 -5.4 volts WIDE 20.0/0.18 Ids0 17.4 -8.6 pA/um LARGE 50/50 Vth 0.43 -0.41 volts Vjbkd 3.1 -4.1 volts Ijlk <50.0 <50.0 pA K' (Uo*Cox/2) 172.8 -36.0 uA/V^2 Low-field Mobility 410.35 85.49 cm^2/V*s COMMENTS: Poly bias varies with design technology. To account for mask bias use the appropriate value for the parameters XL and XW in your SPICE model card. Design Technology XL (um) XW (um) ----------------- ------- ------ SCN6M_DEEP (lambda=0.09) 0.00 -0.01 thick oxide 0.00 -0.01 SCN6M_SUBM (lambda=0.10) -0.02 0.00 thick oxide -0.02 0.00 FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >6.6 <-6.6 volts PROCESS PARAMETERS N+ P+ POLY N+BLK PLY+BLK M1 M2 UNITS Sheet Resistance 6.7 7.7 8.2 61.3 321.5 0.08 0.08 ohms/sq Contact Resistance 10.9 11.4 10.2 4.08 ohms Gate Oxide Thickness 41 angstrom PROCESS PARAMETERS M3 POLY_HRI M4 M5 M6 N_W UNITS Sheet Resistance 0.08 1006.9 0.08 0.08 0.01 933 ohms/sq Contact Resistance 8.43 12.49 16.19 18.33 ohms COMMENTS: BLK is silicide block. CAPACITANCE PARAMETERS N+ P+ POLY M1 M2 M3 M4 M5 M6 R_W D_N_W M5P N_W UNITS Area (substrate) 949 1133 106 37 18 13 8 8 3 130 130 aF/um^2 Area (N+active) 8502 51 20 14 11 9 8 aF/um^2 Area (P+active) 8278 aF/um^2 Area (poly) 60 17 10 7 5 4 aF/um^2 Area (metal1) 38 15 9 7 5 aF/um^2 Area (metal2) 39 15 9 6 aF/um^2 Area (metal3) 39 15 9 aF/um^2 Area (metal4) 37 14 aF/um^2 Area (metal5) 36 1001 aF/um^2 Area (r well) 931 aF/um^2 Area (d well) 574 aF/um^2 Area (no well) 141 aF/um^2 Fringe (substrate) 269 226 -- 59 54 42 24 -- aF/um Fringe (poly) 67 38 29 24 20 18 aF/um Fringe (metal1) 55 35 23 20 aF/um Fringe (metal2) 49 36 28 25 aF/um Fringe (metal3) 54 36 31 aF/um Fringe (metal4) 61 42 aF/um Fringe (metal5) 71 aF/um Overlap (P+active) 635 aF/um