1 3. Aug. 2006
Signal processing systems; Motivation for Digital <-> analog conversion Signal processing systems; Motivation for Digital <-> analog conversion
2 4. Aug. 2006
Continuous and discrete time signals in time and freq. Domain Continuous and discrete time signals and systems
3 8. Aug. 2006
Continuous and discrete time signals in time and freq. Domain DFT; Quantization error distribution and spectral density
4 9. Aug. 2006
DFT; Quantization and sampling DAC(black box) DC characteristics-random mismatch
5 10. Aug. 2006
DFT; Quantization error distribution and spectral density DAC(black box) ac characteristics, measurements; bipolar outputs
6 11. Aug. 2006
DAC system-ideal characteristics, reconstruction filter ADC(black box) dc and dynamic characteristics

15. Aug. 2006 No class

7 16. Aug. 2006
DAC(black box) DC characteristics-random mismatch ADC(black box) measurements-dc sweep, feedback driven input, code density test; ac tests
8 17. Aug. 2006
DAC(black box) ac characteristics, measurements; bipolar outputs Current steering DAC, thermometer, binary weighted
9 18. Aug. 2006
ADC(black box) dc and dynamic characteristics Current steering DAC design-dc characteristics-random mismatch
10 22. Aug. 2006 Assignment #1 due ADC(black box) measurements-dc sweep, feedback driven input, code density test; ac tests Current steering DAC design-random mismatch, systematic errors
11 23. Aug. 2006
ADC(black box) measurements-dc sweep, feedback driven input, code density test; ac tests Current steering DAC design-systematic errors
12 24. Aug. 2006
Delta Sigma modulators-Introduction Current steering DAC layout, optimizing DC characteristics
13 25. Aug. 2006
Delta Sigma modulators-Noise shaping, First order modulator basics Current steering DAC layout, optimizing DC characteristics
14 29. Aug. 2006
Delta Sigma modulators-Derivation of second order modulators Current steering DAC layout, optimizing DC characteristics
15 30. Aug. 2006
Second order Delta Sigma modulators Cascode current sources and their biasing
16 31. Aug. 2006
Delta Sigma modulators-Filter order, stability, MSA Current steering DAC: settling time
17 1. Sep. 2006 Assignment #2 due Delta Sigma modulators-Nbits in the quantizer Current steering DAC: tail node variation-nonlinearity

5. Sep. 2006 No class
Current steering DAC: tail node variation-nonlinearity
18 6. Sep. 2006
Decimation filters for Delta Sigma modulators
19 7. Sep. 2006
Delta sigma modulators: simulation techniques, windowing
20 8. Sep. 2006
Delta Sigma modulators: summary A/D converters-Flash converter block diagram; Bubble correction
21 12. Sep. 2006
Current steering DAC-Thermometer and Binary architectures Flash converter, Bubble correction
22 13. Sep. 2006
Current switches S/H circuits, nonidealities
23 14. Sep. 2006
Differential pair analysis S/H circuits, nonidealities
24 15. Sep. 2006
Effect of current source output resistance-improving Rout S/H circuits, nonidealities
25 19. Sep. 2006
Cascode current sources, biasing
26 20. Sep. 2006
Random mismatch
27 21. Sep. 2006
Random mismatch in current sources-Introduction to systematic mismatch Comparator for resolving logic levels
28 22. Sep. 2006
Optimizing DAC characteristics in the face of systematic and random mismatches Assignment 2 solutions
29 26. Sep. 2006 Assignment #3 due Dynamic element matching; Data weighted averaging Latch-hysteresis, reset, input clocking
30 27. Sep. 2006
Data weighted averaging; Dynamic nonlinearities Assignment 2 solutions
31 28. Sep. 2006
Dynamic nonidealities Preamplifier
32 29. Sep. 2006
Dynamic nonidealities; DAC design summary

30. Sep. 2006 Mid term

33 3. Oct. 2006
A/D converters-Flash converter block diagram; Bubble correction; Midterm paper discussion Interpolation
34 4. Oct. 2006
Flash architecture-bubble correction methods Realization of interpolation

5. Oct. 2006 No class
Preamplifier offset cancellation

6. Oct. 2006 No class

35 10. Oct. 2006
MOS Track and hold circuit, nonidealities Fully differential flash converter; differential difference amplifier
36 11. Oct. 2006
MOS Track and hold circuit, nonidealities, bootstrapping Flash converter summary; Two step A/D converters
37 12. Oct. 2006
Input and output buffers for track and hold circuits
38 13. Oct. 2006
Regenerative latches Digital error correction in two step converters
39 17. Oct. 2006
Need for preamplifiers, offset cancellation Digital error correction; Pipelining of two step converters; Extension to multi step
40 18. Oct. 2006
Offset cancellation in amplifiers; Flash architecture Sources of error and their effects in two step A/D converters
41 19. Oct. 2006
Flash A/D review Switched capacitor amplifiers-introduction, offset cancellation

20. Oct. 2006 No class
Amplifier nonidealities-effect of finite gain

24. Oct. 2006 No class
Assignment 3 solutions
42 25. Oct. 2006
Two step A/D converters-pipelined, subranging Amplifier nonidealities-effect of finite bandwidth; nonlinearity; Single stage opamp
43 26. Oct. 2006
Two step A/D converters-with digital error correction Amplifier, DAC, subtractor combination; Reducing feedback attenuation factor in SC circuits; Pipelined converter timing
44 27. Oct. 2006 Assignment #4 due Two step A/D converters-with digital error correction Subranging converter; Reducing the number of comparators in pipelined converters; 1.5 bit/stage pipeline
45 31. Oct. 2006
Multi step A/D converters and pipelining-Effect of ADC and DAC errors
46 1. Nov. 2006
Switched capacitor amplifiers
47 2. Nov. 2006
Switched capacitor implementation of DAC+amplifier Introduction of Delta-Sigma modulators
48 3. Nov. 2006
Switched capacitor amplifier-effect of finite dc gain Course summary
49 7. Nov. 2006 Presentations, Assignment #5 due

50 8. Nov. 2006 Presentations

51 9. Nov. 2006 Presentations

52 10. Nov. 2006 Presentations

53 14. Nov. 2006 Presentations Switched capacitor amplifier-effect of finite unity gain frequency
54 15. Nov. 2006 Presentations

55 16. Nov. 2006 Presentations

56 17. Nov. 2006 Presentations, Assignment #6 due


21. Nov. 2006 No class


22. Nov. 2006 No class


23. Nov. 2006 No class


24. Nov. 2006 No class


28. Nov. 2006 No class


29. Nov. 2006 Final