Prerequisites

Knowledge of Fourier and Laplace transforms, feedback systems, and CMOS digital gates.

Course contents

This is a self study course. Students are expected to understand the operation of phase locked loops and delay locked loops, block level design of the components in them, and their applications such as frequency synthesizers and clock and data recovery circuits. After this self study, you should

• know the topologies of frequency synthesizers and clock and data recovery circuits at the block level
• be able to calculate the jitter due to noise from different components.
• be able to model the above in verilogA and simulate them

At the end of the semester, you should show simulations of the following:

• Frequency synthesizer with a multi modulus divider(250MHz output from a 5MHz reference)
• Clock and data recovery circuit using a) Linear phase detector, and b) Bang bang phase detector. The input to the clock and data recovery circuit should be a random rectangular bitstream at 250Mb/s passed through a filter H(s) = 1/(1+s/ω_p)⁸ where ω_p/2π = 250MHz

In the final setup, all components other than the VCO can be macromodels. For the VCO, use a 5 stage ring with 3 inverters loading each node(0.18um CMOS technology-get the models from CAD info page). You may use an ideal unity gain VCVS to the control port of the VCO to avoid loading on the controlling stage. Use verilogA in Eldo or Spectre for macro modeling.

At the end of the semester, you will be asked to show the simulation results. In the viva, you will be tested on your understanding of what you did and of PLLs/CDRs in general. i.e. you should be able to explain why you chose the component values the way you did.

Evaluations

• Synopsis: 20%
• Simulation demo: 30%
• Written test: 20% (16th Nov. 2007)
• Viva: 30% (16th Nov. 2007)

References

EE685 lectures on phase locked loops and clock recovery circuits

• PLLs and clock recovery circuits were covered in EE685. You can access the lectures at this link. You'll need to register with a valid e-mail address to receive the password.

Overview

• B. Razavi, "Design of monolithic phase locked loops and clock recovery circuits-A tutorial", Monolithic Phase Locked Loops and Clock Recovery Circuits-Theory and Design, IEEE Press, 1996.

Clock generation

• von Kaenel, V. et al., "A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation", IEEE Journal of Solid-State Circuits, Volume 31, Issue 11, Nov. 1996 Page(s):1715 - 1722
• Gutnik V. et al., "Active GHz clock network using distributed PLLs" IEEE Journal of Solid-State Circuits, Volume 35, Issue 11, Nov. 2000 Page(s):1553 - 1560

RF frequency synthesizers

• Craninckx, J. and Steyaert, M.S.J., "A fully integrated CMOS DCS-1800 frequency synthesizer", IEEE Journal of Solid-State Circuits, Volume 33, Issue 12, Dec. 1998 Page(s):2054 - 2065
• Y Koo et al., "A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems" IEEE Journal of Solid-State Circuits, Volume 37, Issue 5, May 2002 Page(s):536 - 542
• Low-power dividerless frequency synthesis using aperture phase detection Shahani, A.R.; Shaeffer, D.K.; Mohan, S.S.; Samavati, H.; Rategh, H.R.; del Mar Hershenson, M.; Min Xu; Yue, C.P.; Eddleman, D.J.; Horowitz, M.A.; Lee, T.H.; Solid-State Circuits, IEEE Journal of Volume 33, Issue 12, Dec. 1998 Page(s):2232 - 2239

Clock and data recovery

• Clock recovery from random binary signals, JDH Alexander, Electronics Letters, October 1975 (paper, See also page 11-12 of this paper for a brief explanation)
• A self correcting clock recovery circuit, C. R. Hogge, IEEE Journal of Lightwave Technology, December 1985
• A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector Savoj, J.; Razavi, B.; Solid-State Circuits, IEEE Journal of Volume 36, Issue 5, May 2001 Page(s):761 - 768
• A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology Reinhold, M.; Dorschky, C.; Rose, E.; Pullela, R.; Mayer, P.; Kunz, F.; Baeyens, Y.; Link, T.; Mattia, J.-P.; Solid-State Circuits, IEEE Journal of Volume 36, Issue 12, Dec. 2001 Page(s):1937 - 1945
• N. Krishnapura, M. Barazande-Pour, Q. Chaudhry, J. Khoury, K. Lakshmikumar, A. Aggarwal, "A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission", IEEE International Solid State Circuits Conference, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.(paper, slides)

Frequency dividers

• A family of low-power truly modular programmable dividers in standard 0.35-¦Ìm CMOS technology Vaucher, C.S.; Ferencic, I.; Locher, M.; Sedvallson, S.; Voegeli, U.; Wang, Z.; Solid-State Circuits, IEEE Journal of Volume 35, Issue 7, July 2000 Page(s):1039 - 1045
• A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-¦Ìm CMOS Craninckx, J.; Steyaert, M.S.J.; Solid-State Circuits, IEEE Journal of Volume 31, Issue 7, July 1996 Page(s):890 - 897
• N. Krishnapura and P. Kinget, "A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS", IEEE Journal of Solid State Circuits, vol. 35, no. 7, pp. 1019-1024, Jul. 2000. (paper slides)

Simulation

Macromodeling can be done using verilogA in Eldo or Cadence/Spectre. For setup and usage of Eldo, see this page. Eldo's verilogA documentation can be found at $anacad/documentation/eldo_vloga.pdf. Cadence's verilogA documentation can be found at $CDS_INST_DIR/doc/veriaref/veriaref.pdf