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E4332: VLSI Design Laboratory, Spring 2005

Instructor: Nagendra Krishnapura

Class room : Room 833, S. W. Mudd Bldg., 500 W 120th St., New York, NY, 10027.
Class hours : Tuesdays, 6:30pm to 9pm (Note the change in time)
Office : Room 1312, S. W. Mudd Bldg., 500 W 120th St., New York, NY, 10027.
Office hours : Tuesdays, 6:00pm-6:30pm by appointment; send an e-mail
E-mail : nkrishna AT vitesse.com
Mailbox : D7
Phone :
Fax : 1 (212) 932-9421
web page : http://www.ee.iitm.ac.in/~nagendra/E4332/current/courseinfo.html
Lab : Room 1218, S. W. Mudd Bldg., 500 W 120th St., New York, NY, 10027.

Teaching Assistant: Peter Levine

E-mail : plevine AT cisl.columbia.edu
Office : 422 CEPSR, 12th Floor Mudd Labs
Office hours :
Mailbox :
Phone :
Fax : 212-932-9421

Prerequisites

Course : E4321-VLSI Circuits
Knowledge of :

Gate level digital design, design of digital gates and flip-flops, amplifiers, Design of analog and digital building blocks with MOS transistors; use of Cadence circuit design and simulation environment

Course contents

The objective of the course is to design and fabricate a chip. The designs will be fabricated through MOSIS. You will go through all the steps in the design of a chip. You'll start with the conceptual block diagram, design the circuits, simulate them, lay them out, verify the post layout circuit, finish the chip with pads and any other chip finishing procedures, choose a package, and submit the design to MOSIS. You'll get the fabricated chip after 2-3 months. A group of 2 people will work together on a chip.

Process technology

AMI's 0.5um process will be used in this course. The process has 3 metal layers, 2 poly layers, and a high resistivity layer for realizing on chip resistances. Supply voltages upto 5V may be used.

Text book

There is no text book for this class. You can look up some of the suggested references based on the project you choose. You may also need to look at papers in the Journal of Solid State Circuits. IEEE Explore can be used from the computers inside Columbia to download electronic copies of the papers.

Workload(weightage-tentative)

  • Homework(5%): In the beginning there will be a few homeworks in which you will learn the steps involved in design, layout, and verification.
  • Schematic level design and simulations(50%): This is the core of the design and includes the design of the test setup with which you will verify the chip.
  • Submission ready layout(20%): This includes the layout and verification against schematic as well as finishing up the chip with pads and a bonding scheme.
  • Design of a PC board for testing(15%): You will design a PC board for testing using Allegro.
  • Final presentation of the design(10%): You will document your design and give a short presentation.

Computer requirements

Access to the lab in 1218/1235 Mudd for using Cadence circuit simulation software