Integrated Circuits and Systems group, IIT Madras

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
publications:start [2020/03/24 14:35]
nagendra
publications:start [2023/08/24 10:21] (current)
Line 1: Line 1:
 ====== Publications ====== ====== Publications ======
 +===== 2023 =====
 +  * P. Kumar and N. Krishnapura,​ "​Signal-Strength Detector Based on CMOS-Inverter Supply Current,"​ //IEEE Solid-State Circuits Letters//, [[https://​ieeexplore.ieee.org/​document/​10226425|doi:​ 10.1109/​LSSC.2023.3307361]].
 +  * Subha Sarkar, Rajat Agarwal, Nagendra Krishnapura,​ "​Bandpass filter and oscillator ICs with THD < -140dBc at 10Vppd for testing high-resolution ADCs," //2023 International Solid-State Circuits Conference//,​ San Francisco, USA, Feb. 2023. Accepted for presentation. [[https://​ieeexplore.ieee.org/​document/​10067771|doi:​ 10.1109/​ISSCC42615.2023.10067771]].
 +  * S. Ramprasath, M. Madhusudan et al., "A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/​Mixed-Signal Layouts,"​ //ACM Transactions on Design Automation of Electronic Systems//, [[https://​dl.acm.org/​doi/​10.1145/​3580477|doi:​ 10.1145/​3580477]].
 +  * J. Poojary, S. Ramprasath et al., "​Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN,"​ // IEEE Radio Frequency Integrated Circuits Symposium (RFIC)//, San Diego, USA, June 2023. [[https://​doi.org/​10.1109/​RFIC54547.2023.10186141|doi:​ 10.1109/​RFIC54547.2023.10186141]].
  
 +===== 2022 =====
 +  * R. S. A. Kumar, N. Krishnapura and P. Banerjee, "​Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier,"​ //IEEE Journal of Solid-State Circuits//, vol. 57, no. 11, pp. 3384-3395, Nov. 2022, [[https://​ieeexplore.ieee.org/​document/​9777856|doi:​ 10.1109/​JSSC.2022.3171790.]]
 +  * K. M. Vithagan, V. Sundaresha and J. Viraraghavan,​ "​Geometric Programming Approach to Glitch Minimization via Gate Sizing,"​ in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, doi: 10.1109/​TCAD.2022.3207970.
 +  * A. F. Davidson and J. Viraraghavan,​ "​Layout-Based Digital IC Course Projects in Large Classes: Implementation,​ Evaluation, and Plagiarism Detection,"​ in IEEE Transactions on Education, 2022, doi: 10.1109/​TE.2022.3192624. ​
 +  * S. Ramprasath, M. Madhusudan et al., "​Analog/​Mixed-Signal Layout Optimization using Optimal Well Taps," //​International Symposium on Physical Design//, Virtual Event Canada, Apr. 2022. [[https://​dl.acm.org/​doi/​10.1145/​3505170.3506728|doi:​ 10.1145/​3505170.3506728]]
 +  * T. Dhar, S. Ramprasath et al., "A Charge Flow Formulation for Guiding Analog/​Mixed-Signal Placement,"​ //Design, Automation & Test in Europe Conference & Exhibition (DATE)//, Antwerp, Belgium, Mar. 2022. [[https://​doi.org/​10.23919/​DATE54114.2022.9774621|doi:​ 10.23919/​DATE54114.2022.9774621]]
 + 
 +===== 2021 =====
 +  * R. S. A. Kumar, N. Krishnapura and P. Banerjee, "​Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier,"​ //IEEE Journal of Solid-State Circuits//. Early access.
 +  * T. Raviteja and S. Pavan, "Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback,"​ // IEEE Transactions on Circuits and Systems II: Express Briefs//, to appear.
 +  * U Mukherjee, T Halder, A Kannan, S Ghosh, S Pavan,"​A 28.5 µW All-Analog Voice-Activity Detector,"//​ Proceedings of the  IEEE International Symposium on Circuits and Systems//, 2021.
 +  * S. Manivannan and S.Pavan, "A 65-nm CMOS Continuous-Time Pipeline ADC Achieving 70-dB SNDR in 100-MHz Bandwidth,"​ // IEEE Solid-State Circuits Letters//, March 2021.
 +  * S. Pavan, T. Halder and A. Kannan, "​Continuous-Time Incremental Delta-Sigma Modulators with FIR Feedback,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, ​ August 2021.
 +  * S. Pavan and H. Shibata, "​Continuous-Time Pipelined ADCs : A Mini-Tutorial,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, March 2021.
 +  * R. S. A. Kumar and N. Krishnapura,​ "​Multi-Channel Analog-to-Digital Conversion Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, doi: 10.1109/​TCSI.2021.3094679.
 +  * A. Bhat and N. Krishnapura,​ "A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched G<​sub>​m</​sub>​ for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs," //IEEE Transactions on Circuits and Systems I: Regular Papers//, doi: 10.1109/​TCSI.2021.3096843.
 +  *A.Baluni and S.Pavan,"​Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback,"//​IEEE Journal of Solid-State Circuits//, vol. 56, no. 4, Apr. 2021.
 +  * A. Santra and Q. A. Khan, "A High Gain, Low Offset Time-Based Operational Amplifier for Capacitive Loads with 36MHz UGB and 70µA Quiescent Current,"​ //2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)//, 2021, pp. 432-436, doi: 10.1109/​MWSCAS47672.2021.9531892.
 +  * S. Guddanti and Q. A. Khan, "A High Efficiency Fast Transient Zero Output Ripple Buck Converter Using Split PWM Controller with Inductor Mismatch Compensation,"​ //2021 IEEE International Symposium on Circuits and Systems (ISCAS)//, 2021.
 +  * A. Chitnis, R. Chauhan, D. Kaur and Q. Khan, "A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoT," //2021 IEEE Custom Integrated Circuits Conference (CICC)//, 2021.
 +  * A. Nallathambi,​ S. Sen, A. Raghunathan,​ N. Chandrachoodan,​ “Probabilistic spike propagation for efficient hardware implementation of spiking neural networks”,​ Frontiers in Neuroscience,​ vol 15, 2021
 +  * B. N. G. Koneru, N. Chandrachoodan and V. Vasudevan, "A Smoothed LASSO-Based DNN Sparsification Technique,"​ in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4287-4298, Oct. 2021
 +  * B. Vijayakumar and J. Viraraghavan,​ "An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter,"​ 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5, doi: 10.1109/​ISCAS51556.2021.9401131. (Accepted for poster)
  
 ===== 2020 ===== ===== 2020 =====
 +  * S.Billa,​S.Dixit and S.Pavan,"​Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator,"​ //IEEE Journal of Solid-State Circuits//, vol. 55, no. 11, Nov. 2020. 
 +  * I. Mondal and N. Krishnapura,​ "​Effects of AC Response Imperfections in True-Time-Delay Lines,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, [[https://​ieeexplore.ieee.org/​document/​9209153|doi:​ 10.1109/​TCSII.2020.3027529]].
 +  * R.Theertham,​ P.Kootala, S.Billa and S.Pavan, "​Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density," ​ //IEEE Journal of Solid-State Circuits//, vol. 55, no. 9, Sept. 2020. 
 +  * S.Manivannan and S.Pavan,"​Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, October 2020.
 +  * R. S. A. Kumar and N. Krishnapura,​ "​Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, [[https://​ieeexplore.ieee.org/​document/​9169793|doi:​ 10.1109/​TCSI.2020.3013691]].
 +  * Chithra and N. Krishnapura,​ "A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 67, no. 6, pp. 1892-1901, June 2020, [[https://​ieeexplore.ieee.org/​document/​8984721|doi:​ 10.1109/​TCSI.2020.2969977]].
 +  * G. R., J. D. Bandarupalli,​ S. Saxena, "A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).
 +  * S. Mukherjee, A. Das, S. Seth, S. Saxena, "An energy-efficient 3Gb/S PAM4 full-duplex transmitter with 2-tap feed forward equalizer,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).
   * Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, Nagendra Krishnapura,​ "A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).   * Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, Nagendra Krishnapura,​ "A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).
   * Vipul Bajaj, Anand Kannan, Minkle Paul, Nagendra Krishnapura,​ "Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).   * Vipul Bajaj, Anand Kannan, Minkle Paul, Nagendra Krishnapura,​ "Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).
 +  * A. D. Carmine, A. Santra, Q. Khan, "A current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation).
 +  * K. Peetala, A. Ranjan, R. Aenkamreddi,​ Q. Khan, "An Area Efficient, High-Resolution Fully Foldable Switched-Capacitor DC-DC Converter with 16% Efficiency Improvement,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation).
 +  * S. A. Balagopal and J. Viraraghavan,​ "Flash Based In-Memory Multiply-Accumulate Realisation:​ A Theoretical Study,"​ 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-5, doi: 10.1109/​ISCAS45731.2020.9180925. (Accepted for poster)
   * M. V. Praveen and N. Krishnapura,​ "High Linearity Transmit Power Mixers Using Baseband Current Feedback,"​ //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://​ieeexplore.ieee.org/​document/​8889460|doi:​ 10.1109/​JSSC.2019.2945962]]   * M. V. Praveen and N. Krishnapura,​ "High Linearity Transmit Power Mixers Using Baseband Current Feedback,"​ //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://​ieeexplore.ieee.org/​document/​8889460|doi:​ 10.1109/​JSSC.2019.2945962]]
 +  * A.Baluni and S.Pavan, "A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and >100 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC," // IEEE Custom Integrated Circuits Conference (CICC)//, March 2020. **(Outstanding Student Paper Award)**
 +  * H.Shibata,​G.Taylor,​..,​and S.Pavan, "An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter,"​ //IEEE International Solid State Circuits Conference (ISSCC)//, February 2020.
 +  * S Panchapakesan,​ Z Fang, N Chandrachoodan,​ “EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA”, IEEE 28th Intl. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2020
 +  * G Mitra, P K Vairam, Patanjali S., N Chandrachoodan,​ V Kamakoti, “Depending on HTTP/2 for Privacy? Good Luck!”, 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2020
 +  * S Rangachari, N Chandrachoodan,​ “Energy Reduction in Turbo Decoding through Dynamically Varying Bit- Widths”, International Symposium on Circuits and Systems (ISCAS), 2020
 +  * G Vadakkeveedu,​ K Veezhinathan,​ N Chandrachoodan,​ S Potluri, “Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips”,​ IET Comp. & Dig. Techniques 14 (3), 122-131, 2020
 +  * C Dharmaraj, V Vasudevan, N Chandrachoodan,​ “Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders”, ACM Transactions on Embedded Computing Systems (TECS) 20 (2), 1-25, 2020
 +  * C Dharmaraj, V Vasudevan, N Chandrachoodan,​ “Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders”, IET Computers & Digital Techniques 15 (2), 97- 111, 2020
 +
 +
  
 ===== 2019 ===== ===== 2019 =====
Line 24: Line 73:
   * Abhishek Bhat and Nagendra Krishnapura,​ "A 25-to-38GHz,​ 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios,"​ //2019 IEEE International Solid- State Circuits Conference - (ISSCC)//, San Francisco, CA, USA, 2019, pp. 412-414. [[https://​ieeexplore.ieee.org/​document/​8662502|doi:​ 10.1109/​ISSCC.2019.8662502]]   * Abhishek Bhat and Nagendra Krishnapura,​ "A 25-to-38GHz,​ 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios,"​ //2019 IEEE International Solid- State Circuits Conference - (ISSCC)//, San Francisco, CA, USA, 2019, pp. 412-414. [[https://​ieeexplore.ieee.org/​document/​8662502|doi:​ 10.1109/​ISSCC.2019.8662502]]
   * Abirmoya Santra and Qadeer A. Khan, "A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-forward Compensation,"​ //2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)//, Delhi, NCR, India, 2019, pp. 36-40. [[https://​ieeexplore.ieee.org/​document/​8711084|doi:​ 10.1109/​VLSID.2019.00025]]   * Abirmoya Santra and Qadeer A. Khan, "A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-forward Compensation,"​ //2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)//, Delhi, NCR, India, 2019, pp. 36-40. [[https://​ieeexplore.ieee.org/​document/​8711084|doi:​ 10.1109/​VLSID.2019.00025]]
 +  *  B. Xiao et al., "An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier,"​ 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019, pp. 39-42.
 +  * Shivani Bathla, Rahul M. Rao, Nitin Chandrachoodan,​ “A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits”,​ IEEE Trans. VLSI Syst. 27(2): 376-386 (2019)
  
 ===== 2018 ===== ===== 2018 =====
Line 53: Line 104:
   * Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan,​ Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata and Subramanian Iyer "80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity,"​ //IEEE Journal of Solid-State Circuits//, vol. 53, no. 3, pp. 949-960, March 2018. [[https://​ieeexplore.ieee.org/​document/​8252917|doi:​ 10.1109/​JSSC.2017.2784760]]   * Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan,​ Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata and Subramanian Iyer "80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity,"​ //IEEE Journal of Solid-State Circuits//, vol. 53, no. 3, pp. 949-960, March 2018. [[https://​ieeexplore.ieee.org/​document/​8252917|doi:​ 10.1109/​JSSC.2017.2784760]]
   * Q. A. Khan, S. Kim and P. K. Hanumolu, "​Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters — An Alternative to Conventional Analog and Digital Controllers,"​ //2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)//, Pune, 2018, pp. 226-231. [[https://​ieeexplore.ieee.org/​document/​8326930|doi:​ 10.1109/​VLSID.2018.67]]   * Q. A. Khan, S. Kim and P. K. Hanumolu, "​Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters — An Alternative to Conventional Analog and Digital Controllers,"​ //2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)//, Pune, 2018, pp. 226-231. [[https://​ieeexplore.ieee.org/​document/​8326930|doi:​ 10.1109/​VLSID.2018.67]]
 +  * D. Celia, Vinita Vasudevan, Nitin Chandrachoodan,​ “Probabilistic Error Modeling for Two-part Segmented Approximate Adders”, Intl. Symp. On Circ & Systems (ISCAS) 2018.
 +  * Karthikeyan Natarajan, Nitin Chandrachoodan,​ “Lossless Parallel Implementation of a Turbo Decoder on GPU”, High Performance Computing (HiPC) 2018.
 +  * D. Celia, Vinita Vasudevan, Nitin Chandrachoodan,​ “Optimizing power-accuracy trade-offi in approximate adders”, Design, Automation, and Test in Europe (DATE) 2018.
  
 ===== 2017 ===== ===== 2017 =====
Line 73: Line 127:
   * Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava,​ Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura,​ "25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS," //2017 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2017, pp. 434-435. [[https://​ieeexplore.ieee.org/​document/​7870447|doi:​ 10.1109/​ISSCC.2017.7870447]]   * Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava,​ Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura,​ "25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS," //2017 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2017, pp. 434-435. [[https://​ieeexplore.ieee.org/​document/​7870447|doi:​ 10.1109/​ISSCC.2017.7870447]]
   * R. S. Ashwin Kumar and Nagendra Krishnapura,​ "A Low Power Multi-channel Input Delta-Sigma ADC without Reset,"​ //2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)//, Hyderabad, 2017, pp. 9-14. [[https://​ieeexplore.ieee.org/​document/​7884750|doi:​ 10.1109/​VLSID.2017.85]]   * R. S. Ashwin Kumar and Nagendra Krishnapura,​ "A Low Power Multi-channel Input Delta-Sigma ADC without Reset,"​ //2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)//, Hyderabad, 2017, pp. 9-14. [[https://​ieeexplore.ieee.org/​document/​7884750|doi:​ 10.1109/​VLSID.2017.85]]
 +  * Sundarrajan Rangachari, Jaiganesh Balakrishnan,​ Nitin Chandrachoodan,​ “Scenario-Aware Dynamic Power Reduction Using Bias Addition”,​ IEEE Transactions on VLSI Systems, vol. 25, no. 2, Feb 2017
  
 ===== 2016 ===== ===== 2016 =====
Line 86: Line 141:
   * A. Jain and S. Pavan, "A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback,"​ //2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)//,​ Honolulu, HI, 2016, pp. 1-2. [[https://​ieeexplore.ieee.org/​document/​7573466|doi:​ 10.1109/​VLSIC.2016.7573466]]  ​   * A. Jain and S. Pavan, "A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback,"​ //2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)//,​ Honolulu, HI, 2016, pp. 1-2. [[https://​ieeexplore.ieee.org/​document/​7573466|doi:​ 10.1109/​VLSIC.2016.7573466]]  ​
   * S. Pavan and R. Rajan, "​Design Considerations for Filtering Delta Sigma Converters",​ //​Proceedings of the Workshop on  Advanced Analog Circuit Design//, 24th-27th April 2016, Villach, Austria. [[https://​doi.org/​10.1007/​978-3-319-41670-0_4]]   * S. Pavan and R. Rajan, "​Design Considerations for Filtering Delta Sigma Converters",​ //​Proceedings of the Workshop on  Advanced Analog Circuit Design//, 24th-27th April 2016, Villach, Austria. [[https://​doi.org/​10.1007/​978-3-319-41670-0_4]]
 +  * Anandha Ruban T T, Preetam Tadeparthy, Sankaran Aniruddhan, Vikram Gakhar, and Muthusubramanian Venkateswaran,​ "​Optimal dynamic phase add/drop mechanism in multiphase DC-DC buck converters,"​ //2016 IEEE Applied Power Electronics Conference and Exposition (APEC)//, Long Beach, USA, 20-24 March 2016. [[https://​ieeexplore.ieee.org/​stamp/​stamp.jsp?​tp=&​arnumber=7468124|doi:​ 10.1109/​APEC.2016.7468124]]
   * S. Billa, A. Sukumaran and S. Pavan, "15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts,"​ //2016 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2016, pp. 276-277. [[https://​ieeexplore.ieee.org/​document/​7418014|doi:​ 10.1109/​ISSCC.2016.7418014]]   * S. Billa, A. Sukumaran and S. Pavan, "15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts,"​ //2016 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2016, pp. 276-277. [[https://​ieeexplore.ieee.org/​document/​7418014|doi:​ 10.1109/​ISSCC.2016.7418014]]
   * K. Singh and S. Pavan, "A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition,"​ //2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)//, Kolkata, 2016, pp. 230-235. [[https://​ieeexplore.ieee.org/​document/​7434957|doi:​ 10.1109/​VLSID.2016.21]]   * K. Singh and S. Pavan, "A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition,"​ //2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)//, Kolkata, 2016, pp. 230-235. [[https://​ieeexplore.ieee.org/​document/​7434957|doi:​ 10.1109/​VLSID.2016.21]]
Line 93: Line 149:
   * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, "A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition,"​ //IEEE Journal of Solid-State Circuits//, vol. 51, no. 2, pp. 428-439, Feb. 2016. [[https://​ieeexplore.ieee.org/​document/​7362125|doi:​ 10.1109/​JSSC.2015.2497963]]   * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, "A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition,"​ //IEEE Journal of Solid-State Circuits//, vol. 51, no. 2, pp. 428-439, Feb. 2016. [[https://​ieeexplore.ieee.org/​document/​7362125|doi:​ 10.1109/​JSSC.2015.2497963]]
   * G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar,​ R. Nandwana, and P. K. Hanumolu, "23.1 A 16Mb/​s-to-8Gb/​s 14.1-to-5.9pJ/​b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS," //2016 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2016, pp. 398-399. [[https://​ieeexplore.ieee.org/​document/​7418075|doi:​ 10.1109/​ISSCC.2016.7418075]]   * G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar,​ R. Nandwana, and P. K. Hanumolu, "23.1 A 16Mb/​s-to-8Gb/​s 14.1-to-5.9pJ/​b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS," //2016 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2016, pp. 398-399. [[https://​ieeexplore.ieee.org/​document/​7418075|doi:​ 10.1109/​ISSCC.2016.7418075]]
 +  * Celia Dharmaraj and Nitin Chandrachoodan,​ “Guided Multilevel Approximation of Less Significant Bits for Power Reduction”,​ Intl. Symposium on VLSI Design and Test (VDAT), 2016. 
 +  * Amit Salaskar, Nitin Chandrachoodan,​ “FFT/IFFT implementation using Vivado HLS”, Intl. Sym. On VLSI Des. & Test (VDAT) 2016.
 ===== 2015 ===== ===== 2015 =====
   * J. d. l. Rosa, K. Pun, R. Schreier, and S. Pavan, "​Next-Generation Delta-Sigma Converters: Trends and Perspectives,"​ //IEEE Journal on Emerging and Selected Topics in Circuits and Systems//, vol. 5, no. 4, pp. 484-499, Dec. 2015. [[https://​ieeexplore.ieee.org/​document/​7343753|doi:​ 10.1109/​JETCAS.2015.2502164]] ​     * J. d. l. Rosa, K. Pun, R. Schreier, and S. Pavan, "​Next-Generation Delta-Sigma Converters: Trends and Perspectives,"​ //IEEE Journal on Emerging and Selected Topics in Circuits and Systems//, vol. 5, no. 4, pp. 484-499, Dec. 2015. [[https://​ieeexplore.ieee.org/​document/​7343753|doi:​ 10.1109/​JETCAS.2015.2502164]] ​  
 +  * S. Potluri, A. S. Trinadh, S. Babu, V. Kamakoti and N. Chandrachoodan,​ “DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-on-Shift ​ At-Speed Testing”, ACM Transactions on Design Automation of Electronic Systems, vol. 21, no. 1, Nov 2015
 +  * Chaitanya Peddawad, Aman Goel, B. Dheeraj, Nitin Chandrachoodan,​“iitRACE:​ A Memory Effiicient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal”, ICCAD 2015.
   * Amrith Sukumaran and Shanthi Pavan, "A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC," //ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)//,​ Graz, 2015, pp. 217-220. [[https://​ieeexplore.ieee.org/​document/​7313866|doi:​ 10.1109/​ESSCIRC.2015.7313866]]   * Amrith Sukumaran and Shanthi Pavan, "A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC," //ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)//,​ Graz, 2015, pp. 217-220. [[https://​ieeexplore.ieee.org/​document/​7313866|doi:​ 10.1109/​ESSCIRC.2015.7313866]]
   * Imon Mondal and Nagendra Krishnapura,​ "Gain enhanced high frequency OTA with on-chip tuned negative conductance load," //2015 IEEE International Symposium on Circuits and Systems (ISCAS)//, Lisbon, 2015, pp. 2085-2088. [[https://​ieeexplore.ieee.org/​document/​7169089|doi:​ 10.1109/​ISCAS.2015.7169089]]   * Imon Mondal and Nagendra Krishnapura,​ "Gain enhanced high frequency OTA with on-chip tuned negative conductance load," //2015 IEEE International Symposium on Circuits and Systems (ISCAS)//, Lisbon, 2015, pp. 2085-2088. [[https://​ieeexplore.ieee.org/​document/​7169089|doi:​ 10.1109/​ISCAS.2015.7169089]]
Line 387: Line 446:
  
 ====== Patents ====== ====== Patents ======
 +  * P. Yadav and S. Ramprasath, " Keep-through regions for handling end-of-line rules in routing,"​ US 11,586,796 B1, Feb. 21, 2023. [[https://​patents.google.com/​patent/​US11586796B1|US11586796B1]]
   * M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker and T. Sutton, "​Current measurments in switching regulators",​ US 9,755,518, September 5, 2017. [[https://​patents.google.com/​patent/​US9755518|US9755518B2]]   * M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker and T. Sutton, "​Current measurments in switching regulators",​ US 9,755,518, September 5, 2017. [[https://​patents.google.com/​patent/​US9755518|US9755518B2]]
   * M. Bansal, Q. Khan and C. Shi, "​Average current mode control of multi-phase switching power converters,"​ US 9,442,140, Sep. 13, 2016. [[https://​patents.google.com/​patent/​JP6185194B2/​en|JP6185194B2]]   * M. Bansal, Q. Khan and C. Shi, "​Average current mode control of multi-phase switching power converters,"​ US 9,442,140, Sep. 13, 2016. [[https://​patents.google.com/​patent/​JP6185194B2/​en|JP6185194B2]]