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| ====== Publications ====== | ====== Publications ====== | ||
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| ===== 2020 ===== | ===== 2020 ===== | ||
| + | * G. R., J. D. Bandarupalli, S. Saxena, "A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | ||
| + | * S. Mukherjee, A. Das, S. Seth, S. Saxena, "An energy-efficient 3Gb/S PAM4 full-duplex transmitter with 2-tap feed forward equalizer," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | ||
| * Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, Nagendra Krishnapura, "A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | * Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, Nagendra Krishnapura, "A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | ||
| * Vipul Bajaj, Anand Kannan, Minkle Paul, Nagendra Krishnapura, "Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | * Vipul Bajaj, Anand Kannan, Minkle Paul, Nagendra Krishnapura, "Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | ||
| + | * A. D. Carmine, A. Santra, Q. Khan, "A current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). | ||
| + | * K. Peetala, A. Ranjan, R. Aenkamreddi, Q. Khan, "An Area Efficient, High-Resolution Fully Foldable Switched-Capacitor DC-DC Converter with 16% Efficiency Improvement," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). | ||
| * M. V. Praveen and N. Krishnapura, "High Linearity Transmit Power Mixers Using Baseband Current Feedback," //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://ieeexplore.ieee.org/document/8889460|doi: 10.1109/JSSC.2019.2945962]] | * M. V. Praveen and N. Krishnapura, "High Linearity Transmit Power Mixers Using Baseband Current Feedback," //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://ieeexplore.ieee.org/document/8889460|doi: 10.1109/JSSC.2019.2945962]] | ||
| ===== 2019 ===== | ===== 2019 ===== | ||
| * R. S. A. Kumar and N. Krishnapura, "A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter," //ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)//, Cracow, Poland, 2019, pp. 365-368. [[https://ieeexplore.ieee.org/document/8902610|doi: 10.1109/ESSCIRC.2019.8902610]] | * R. S. A. Kumar and N. Krishnapura, "A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter," //ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)//, Cracow, Poland, 2019, pp. 365-368. [[https://ieeexplore.ieee.org/document/8902610|doi: 10.1109/ESSCIRC.2019.8902610]] | ||
| - | * N. Krishnapura, A. N. Bhat, S. Mukherjee, K. A. Shrivastava and M. Bonu, "Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables," //IEEE Transactions on Circuits and Systems I: Regular Papers//, 2019. doi: 10.1109/TCSI.2019.2926143. | + | * N. Krishnapura, A. N. Bhat, S. Mukherjee, K. A. Shrivastava and M. Bonu, "Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 9, pp. 3531-3543, Sept. 2019. [[https://ieeexplore.ieee.org/document/8777122|doi: 10.1109/TCSI.2019.2926143]] |
| - | * S. Kumar, R. Goroju, D. K. Bhat, K. S. Rakshitdatta and N. Krishnapura, "Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs," //IEEE Transactions on Circuits and Systems I: Regular Papers//, 2019. doi: 10.1109/TCSI.2019.2926927. | + | * S. Kumar, R. Goroju, D. K. Bhat, K. S. Rakshitdatta and N. Krishnapura, "Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 9, pp. 3393-3401, Sept. 2019. [[https://ieeexplore.ieee.org/document/8766899|doi: 10.1109/TCSI.2019.2926927]] |
| - | * Shanthi Pavan and Raviteja Theertham, "Improved offline calibration of DAC errors in Delta Sigma data converters," // IEEE Transactions on Circuits and Systems: Express Briefs,// (to appear). | + | * Shanthi Pavan and Raviteja Theertham, "Improved offline calibration of DAC errors in Delta Sigma data converters," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 10, pp. 1618-1622, Oct. 2019. [[https://ieeexplore.ieee.org/document/8733905|doi: 10.1109/TCSII.2019.2921777]] |
| - | * Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, and Shanthi Pavan, "Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezo Electric Energy Harvesting," // IEEE Journal of Solid State Circuits,// (to appear). | + | * Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, and Shanthi Pavan, "Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezo Electric Energy Harvesting," //IEEE Journal of Solid-State Circuits//, vol. 54, no. 9, pp. 2590-2600, Sept. 2019. [[https://ieeexplore.ieee.org/document/8741086|doi: 10.1109/JSSC.2019.2917158]] |
| - | * Raviteja Theertham, Prasanth Kootala, Sujith Billa, and Shanthi Pavan, "A 24mW chopped CTDSM achieving 103.5dB SNDR and 107.5dB DR in a 250kHz bandwidth," // IEEE Symposium on VLSI Circuits, Kyoto, Japan //, June 2019. | + | * Raviteja Theertham, Prasanth Kootala, Sujith Billa, and Shanthi Pavan, "A 24mW chopped CTDSM achieving 103.5dB SNDR and 107.5dB DR in a 250kHz bandwidth," //2019 Symposium on VLSI Circuits//, Kyoto, Japan, 2019, pp. C226-C227. [[https://ieeexplore.ieee.org/document/8778026|doi: 10.23919/VLSIC.2019.8778026]] |
| - | * Raviteja Theertham and Shanthi Pavan, "Unified analysis, modeling, and simulation of chopping artifacts in continuous-time delta-sigma converters," // IEEE Transactions on Circuits and Systems: Regular Papers //, August 2019. | + | * Raviteja Theertham and Shanthi Pavan, "Unified analysis, modeling, and simulation of chopping artifacts in continuous-time delta-sigma converters," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 8, pp. 2831-2842, Aug. 2019. [[https://ieeexplore.ieee.org/document/8698838|doi: 10.1109/TCSI.2019.2907167]] |
| - | * Kishalay Dutta, Vinod Menezes and Shanthi Pavan, "Analysis and design of cyclic switched-capacitor DC-DC converters," // IEEE Transactions on Circuits and Systems: Regular Papers //, August 2019. | + | * Kishalay Dutta, Vinod Menezes and Shanthi Pavan, "Analysis and design of cyclic switched-capacitor DC-DC converters," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 8, pp. 3227-3237, Aug. 2019. [[https://ieeexplore.ieee.org/document/8698873|doi: 10.1109/TCSI.2019.2907309]] |
| - | * Saravana Manivannan and Shanthi Pavan, "Degradation of alias rejection in continuous-time bandpass delta-sigma converters due to weak loop filter nonlinearities," //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. | + | * Saravana Manivannan and Shanthi Pavan, "Degradation of alias rejection in continuous-time bandpass delta-sigma converters due to weak loop filter nonlinearities," //2019 IEEE International Symposium on Circuits and Systems (ISCAS)//, Sapporo, Japan, 2019, pp. 1-5. [[https://ieeexplore.ieee.org/document/8702763|doi: 10.1109/ISCAS.2019.8702763]] |
| - | * Shanthi Pavan, "Simplified analysis of total integrated noise in passive switched-capacitor and N-path filters," //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. | + | * Shanthi Pavan, "Simplified analysis of total integrated noise in passive switched-capacitor and N-path filters," //2019 IEEE International Symposium on Circuits and Systems (ISCAS)//, Sapporo, Japan, 2019, pp. 1-5. [[https://ieeexplore.ieee.org/document/8702129|doi: 10.1109/ISCAS.2019.8702129]] |
| - | * Shanthi Pavan, "An alternative approach to Bode's Noise Theorem," // IEEE Transactions on Circuits and Systems: Express Briefs//, May 2019. | + | * Shanthi Pavan, "An alternative approach to Bode's Noise Theorem," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 5, pp. 738-742, May 2019. [[https://ieeexplore.ieee.org/document/8675338|doi: 10.1109/TCSII.2019.2907860]] |
| - | * Abirmoya Santra, Angelo De Carmine, Guttha Venkata Sesha Rao, Qadeer A. Khan, "A Highly Scalable, Time-Based Capless Low-Dropout Regulator Using Master-Slave Domino Control," //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. (Accepted for presentation). | + | * Abirmoya Santra, Angelo De Carmine, Guttha Venkata Sesha Rao, Qadeer A. Khan, "A Highly Scalable, Time-Based Capless Low-Dropout Regulator Using Master-Slave Domino Control," //2019 IEEE International Symposium on Circuits and Systems (ISCAS)//, Sapporo, Japan, 2019, pp. 1-4. [[https://ieeexplore.ieee.org/document/8702457|doi: 10.1109/ISCAS.2019.8702457]] |
| - | * Chithra and Nagendra Krishnapura, "Static Phase Offset Reduction Technique for Delay Locked Loops," //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. (Accepted for presentation). | + | * Chithra and Nagendra Krishnapura, "Static Phase Offset Reduction Technique for Delay Locked Loops," //2019 IEEE International Symposium on Circuits and Systems (ISCAS)//, Sapporo, Japan, 2019, pp. 1-5. [[https://ieeexplore.ieee.org/document/8702613|doi: 10.1109/ISCAS.2019.8702613]] |
| - | * Chithra and Nagendra Krishnapura, "Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design," //2019 IEEE International Conference on Modeling of Systems, Circuits, and Devices (MOS-AK India 2019)//, Hyderabad, Feb. 2019. | + | * Chithra and Nagendra Krishnapura, "Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design," //2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)//, Hyderabad, India, 2019, pp. 1-6. [[https://ieeexplore.ieee.org/document/8902447|doi: 10.1109/MOS-AK.2019.8902447]] |
| - | * Abhishek Bhat and Nagendra Krishnapura, "A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios," //2019 International Solid-State Circuits Conference//, San Francisco, Feb. 2019. | + | * Abhishek Bhat and Nagendra Krishnapura, "A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios," //2019 IEEE International Solid- State Circuits Conference - (ISSCC)//, San Francisco, CA, USA, 2019, pp. 412-414. [[https://ieeexplore.ieee.org/document/8662502|doi: 10.1109/ISSCC.2019.8662502]] |
| - | * Abirmoya Santra, Qadeer A. Khan, "A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-forward Compensation," //32nd International Conference on VLSI Design//, New Delhi, India, Jan. 2019. | + | * Abirmoya Santra and Qadeer A. Khan, "A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-forward Compensation," //2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)//, Delhi, NCR, India, 2019, pp. 36-40. [[https://ieeexplore.ieee.org/document/8711084|doi: 10.1109/VLSID.2019.00025]] |
| ===== 2018 ===== | ===== 2018 ===== | ||
| - | * Harikumar Ganesan, Boby George, Sankaran Aniruddhan and Saleem Haneefa, "A Dual Slope LVDT-to-Digital Converter", //IEEE Sensors Journal//, 2018, early access. | + | * Harikumar Ganesan, Boby George, Sankaran Aniruddhan and Saleem Haneefa, "A Dual Slope LVDT-to-Digital Converter," //IEEE Sensors Journal//, vol. 19, no. 3, pp. 868-876, 1 Feb.1, 2019. [[https://ieeexplore.ieee.org/document/8517138|doi: 10.1109/JSEN.2018.2878883]] |
| - | * Anantha MS, Abhishek Kumar and Sankaran Aniruddhan, "A Compact +10/+5dBm 800/2600MHz LTE Driver Amplifier with Ground-Bounce Reduction", //IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)//, 2018, early access. | + | * Anantha MS, Abhishek Kumar and Sankaran Aniruddhan, "A Compact +10/+5dBm 800/2600MHz LTE Driver Amplifier with Ground-Bounce Reduction," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 6, pp. 919-923, June 2019. [[https://ieeexplore.ieee.org/document/8477034|doi: 10.1109/TCSII.2018.2873053]] |
| - | * Arpan Thakkar, Srinivas Theertham and Sankaran Aniruddhan, "Phase Noise Analysis of Bipolar Class-C VCOs with Delay in Oscillator Loop", //IEEE Transactions on Very Large Scale Integration (VLSI) Systems//, 2018, early access. | + | * Arpan Thakkar, Srinivas Theertham and Sankaran Aniruddhan, "Phase Noise Analysis of Bipolar Class-C VCOs with Delay in Oscillator Loop," //IEEE Transactions on Very Large Scale Integration (VLSI) Systems//, vol. 26, no. 12, pp. 2873-2883, Dec. 2018. [[https://ieeexplore.ieee.org/document/8471115|doi: 10.1109/TVLSI.2018.2861818]] |
| - | * Ahmad Sharkia, Sankaran Aniruddhan, Shahriar Mirabbasi and Sudip Shekhar, "A Compact, Voltage-Mode Type-I PLL with Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter", //IEEE Transactions on Circuits and Systems I//, 2018, early access. | + | * Ahmad Sharkia, Sankaran Aniruddhan, Shahriar Mirabbasi and Sudip Shekhar, "A Compact, Voltage-Mode Type-I PLL with Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 1, pp. 43-53, Jan. 2019. [[https://ieeexplore.ieee.org/document/8432060|doi: 10.1109/TCSI.2018.2858197]] |
| - | * G. Vinodhini, Boby George, Sankaran Aniruddhan, J. Dhurga Devi and P.V. Ramakrishna, "Performance Analysis of Oscillator Based Read-out Circuit for LVDT", //IEEE Transactions on Instrumentation & Measurement//, 2018, early access. | + | * G. Vinodhini, Boby George, Sankaran Aniruddhan, J. Dhurga Devi and P.V. Ramakrishna, "Performance Analysis of Oscillator Based Read-out Circuit for LVDT," //IEEE Transactions on Instrumentation and Measurement//, vol. 68, no. 4, pp. 1080-1088, April 2019. [[https://ieeexplore.ieee.org/document/8434261|doi: 10.1109/TIM.2018.2858038]] |
| - | * R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura, "Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion," //IEEE Transactions on Circuits and Systems I: Regular Papers//, 2018. DOI: 10.1109/TCSI.2018.2854707. | + | * R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura, "Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 11, pp. 3651-3661, Nov. 2018. [[https://ieeexplore.ieee.org/document/8428537|doi: 10.1109/TCSI.2018.2854707]] |
| - | * Abhishek Bhat and Nagendra Krishnapura, "On-Chip Static Phase Difference Measurement Circuit with Gain and Offset Calibration," //IEEE Transactions on Circuits and Systems II: Express Briefs//, 2018. DOI: 10.1109/TCSII.2018.2842101. | + | * Abhishek Bhat and Nagendra Krishnapura, "On-Chip Static Phase Difference Measurement Circuit with Gain and Offset Calibration," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 2, pp. 162-166, Feb. 2019. [[https://ieeexplore.ieee.org/document/8369120|doi: 10.1109/TCSII.2018.2842101]] |
| - | * S.Manivannan and S.Pavan,"Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities,"//IEEE Transactions on Circuits and Systems: Regular Papers//, October 2018. | + | * S.Manivannan and S.Pavan, "Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 10, pp. 3207-3215, Oct. 2018. [[https://ieeexplore.ieee.org/document/8371270|doi: 10.1109/TCSI.2018.2826443]] |
| - | * S.Pavan and E.Klumperink, "Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network,"//IEEE Transactions on Circuits and Systems: Regular Papers//, October 2018. | + | * S.Pavan and E.Klumperink, "Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 10, pp. 3267-3278, Oct. 2018. [[https://ieeexplore.ieee.org/document/8336915|doi: 10.1109/TCSI.2018.2816342]] |
| - | * S. Javvaji, V.Singhal, V.Menezes and S.Pavan,"Multi-step bias flip rectification for piezo-electric energy harvesting,"//Proceedings of the European Solid State Circuits Conference, Dresden, Germany//, Sept. 2018. | + | * S. Javvaji, V.Singhal, V.Menezes and S.Pavan, "Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting," //ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)//, Dresden, 2018, pp. 42-45. [[https://ieeexplore.ieee.org/document/8494272|doi: 10.1109/ESSCIRC.2018.8494272]] |
| - | * A. Kumar and S. Aniruddhan,"A 2.5GHz CMOS Full-Duplex Front-End for Asymmetric Data Networks,"//IEEE Transactions on Circuits and Systems: Regular Papers//, October 2018. | + | * A. Kumar and S. Aniruddhan,"A 2.5GHz CMOS Full-Duplex Front-End for Asymmetric Data Networks," // IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 10, pp. 3174-3185, Oct. 2018. [[https://ieeexplore.ieee.org/document/8315501|doi: 10.1109/TCSI.2018.2809924]] |
| - | * S.Pavan, "Improved Chopping in Continuous-time Delta-Sigma Converters using FIR Feedback and N-Path Techniques,"//IEEE Transactions on Circuits and Systems: Express Briefs//, May 2018 (ISCAS 2018 Special Issue). | + | * S. Pavan, "Improved Chopping in Continuous-Time Delta–Sigma Converters Using FIR Feedback and ${N}$ -Path Techniques," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 65, no. 5, pp. 552-556, May 2018. [[https://ieeexplore.ieee.org/document/8326528|doi: 10.1109/TCSII.2018.2820017]] |
| - | * S.Pavan and S.Baskaran, "What Architecture Should I use for my Continuous-time Delta-Sigma Converter?,"// Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//Florence. | + | * S. Pavan and S. Baskaran, "What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator?," //2018 IEEE International Symposium on Circuits and Systems (ISCAS)//, Florence, 2018, pp. 1-5. [[https://ieeexplore.ieee.org/document/8351141|doi: 10.1109/ISCAS.2018.8351141]] |
| - | * Peeyoosh Mirajkar, Jagdish Chand, Sankaran Aniruddhan, Srinivas Theertham, "Low Phase Noise Ku-Band VCO with Reduced Frequency Drift Across Temperature,"// Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//Florence. | + | * P. Mirajkar, J. Chand, S. Aniruddhan and S. Theertham, "Low Phase Noise Ku-Band VCO with Reduced Frequency Drift Across Temperature," //2018 IEEE International Symposium on Circuits and Systems (ISCAS)//, Florence, 2018, pp. 1-5. [[https://ieeexplore.ieee.org/document/8351140|doi: 10.1109/ISCAS.2018.8351140]] |
| - | * Arpan Sureshbhai Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Jagdish Chand Goyal, Sankaran Aniruddhan, "A 27.2GHz Bipolar LC-VCO Using Class-C Biasing to Maximize Achievable Fosc in 130nm BiCMOS,"// Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//Florence. | + | * A. Thakkar, S. Theertham, P. Mirajkar, J. C. Goyal and S. Aniruddhan, "A 27.2GHz bipolar LC-VCO using class-C biasing to maximize achievable Fosc in 130nm BiCMOS," //2018 IEEE International Symposium on Circuits and Systems (ISCAS)//, Florence, 2018, pp. 1-5. [[https://ieeexplore.ieee.org/document/8351527|doi: 10.1109/ISCAS.2018.8351527]] |
| - | * Abhishek Kumar, Radha Krishna Ganti, Sankaran Aniruddhan, "A Same-Channel Full-Duplex Receiver Using Direct RF Sampling,"// Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//Florence. | + | * A. Kumar, R. K. Ganti and S. Aniruddhan, "A Same-Channel Full-Duplex Receiver Using Direct RF Sampling," //2018 IEEE International Symposium on Circuits and Systems (ISCAS)//, Florence, 2018, pp. 1-4. [[https://ieeexplore.ieee.org/document/8351676|doi: 10.1109/ISCAS.2018.8351676]] |
| - | * Qadeer A. Khan, Saurabh Saxena, Abirmoya Santra, "Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier, "// Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//Florence. | + | * Q. A. Khan, S. Saxena and A. Santra, "Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier," //2018 IEEE International Symposium on Circuits and Systems (ISCAS)//, Florence, 2018, pp. 1-5. [[https://ieeexplore.ieee.org/document/8351598|doi: 10.1109/ISCAS.2018.8351598]] |
| - | * S.Pavan,"FIR Feedback in Continuous-time Delta Sigma Converters,"// Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,//San Diego. | + | * S. Pavan, "Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters," //2018 IEEE Custom Integrated Circuits Conference (CICC)//, San Diego, CA, 2018, pp. 1-8. [[https://ieeexplore.ieee.org/document/8357084|doi: 10.1109/CICC.2018.8357084]] |
| - | * S.Manivannan and S.Pavan,"A 1 MHz Bandwidth, Filtering Continuous-Time Delta-Sigma ADC with 36 dBFS Out-of-Band IIP3 and 76 dB SNDR,"// Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,//San Diego. | + | * S. Manivannan and S. Pavan, "A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR," //2018 IEEE Custom Integrated Circuits Conference (CICC)//, San Diego, CA, 2018, pp. 1-4. [[https://ieeexplore.ieee.org/document/8357089|doi: 10.1109/CICC.2018.8357089]] |
| - | * S.Pavan,"Practical Design and Simulation Techniques for Continuous-time Delta Sigma Converters,"// Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,//San Diego. | + | * S. Pavan, "Practical design and simulation techniques for continuous-time ΔΣ converters," //2018 IEEE Custom Integrated Circuits Conference (CICC)//, San Diego, CA, 2018, pp. 1-81. [[https://ieeexplore.ieee.org/document/8357104|doi: 10.1109/CICC.2018.8357104]] |
| - | * I. Mondal and N. Krishnapura, "Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters," //IEEE Transactions on Circuits and Systems I: Regular Papers//, To appear. DOI: 10.1109/TCSI.2018.2799080 | + | * I. Mondal and N. Krishnapura, "Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 9, pp. 2703-2714, Sept. 2018. [[https://ieeexplore.ieee.org/document/8287809|doi: 10.1109/TCSI.2018.2799080]] |
| - | * Abhishek Bhat and Nagendra Krishnapura, "Low 1/f<sup>3</sup> Phase Noise Quadrature LC VCOs", //IEEE Transactions on Circuits and Systems: Regular Papers//, To appear. DOI: 10.1109/TCSI.2017.2782247 | + | * A. Bhat and N. Krishnapura, "Low $1/f^{3}$ Phase Noise Quadrature LC VCOs," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 7, pp. 2127-2138, July 2018. [[https://ieeexplore.ieee.org/document/8245875|doi: 10.1109/TCSI.2017.2782247]] |
| - | * S.Pavan and E.Klumperink, "Analysis of the Effect of Source Capacitance and Inductance on N-path Mixers and Filters,"//IEEE Transactions on Circuits and Systems: Regular Papers//, May 2018. | + | * S. Pavan and E. Klumperink, "Analysis of the Effect of Source Capacitance and Inductance on $N$ -Path Mixers and Filters," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 5, pp. 1469-1480, May 2018. [[https://ieeexplore.ieee.org/document/8066456|doi: 10.1109/TCSI.2017.2754342]] |
| - | * P. Mirajkar, J. Chand, S. Aniruddhan and S. Theertham,"Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design,"//IEEE Transactions on Very Large Scale Integration (VLSI) Systems//, vol. 26, no.3, March 2018. | + | * P. Mirajkar, J. Chand, S. Aniruddhan and S. Theertham, "Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design," //IEEE Transactions on Very Large Scale Integration (VLSI) Systems//, vol. 26, no. 3, pp. 589-593, March 2018. [[https://ieeexplore.ieee.org/document/8166816|doi: 10.1109/TVLSI.2017.2769709]] |
| - | * A.Jain and S. Pavan, "Continuous-time delta-sigma modulators with time-interleaved FIR feedback,"//IEEE Transactions on Circuits and Systems: Regular Papers//, Feb. 2018. | + | * A. Jain and S. Pavan, "Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 2, pp. 434-443, Feb. 2018. [[https://ieeexplore.ieee.org/document/8030132|doi: 10.1109/TCSI.2017.2740287]] |
| - | * Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian Iyer "80Kb Logic Embedded High-K Charge Trap Transistor based Multi-Time-Programmable Memory with no Added Process Complexity" IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 949-960, March 2018. | + | * Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata and Subramanian Iyer "80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity," //IEEE Journal of Solid-State Circuits//, vol. 53, no. 3, pp. 949-960, March 2018. [[https://ieeexplore.ieee.org/document/8252917|doi: 10.1109/JSSC.2017.2784760]] |
| - | * Qadeer. A. Khan, S. Kim and Pavan. K. Hanumolu, "Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters — An Alternative to Conventional Analog and Digital Controllers," //31st International Conference on VLSI Design (VLSID)//, Pune, Jan. 2018. | + | * Q. A. Khan, S. Kim and P. K. Hanumolu, "Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters — An Alternative to Conventional Analog and Digital Controllers," //2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)//, Pune, 2018, pp. 226-231. [[https://ieeexplore.ieee.org/document/8326930|doi: 10.1109/VLSID.2018.67]] |
| ===== 2017 ===== | ===== 2017 ===== | ||
| - | * Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Hairong Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil and Shanthi Pavan, "A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving −164-dBFS/Hz NSD," //IEEE Journal of Solid State Circuits//, December 2017. | + | * Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Hairong Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil and Shanthi Pavan, "A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving −164-dBFS/Hz NSD," //IEEE Journal of Solid-State Circuits//, vol. 52, no. 12, pp. 3219-3234, Dec. 2017. [[https://ieeexplore.ieee.org/document/8052223|doi: 10.1109/JSSC.2017.2747128]] |
| - | * Gaurav Agrawal and Sankaran Aniruddhan, "A Modified Bias Scheme for High-Gain Low-Noise Folded Cascode OTAs",// IEEE Electron Devices and Solid-State Circuits Conference (EDSSC 2017), October 2017//Hsinchu, Taiwan. | + | * Gaurav Agrawal and Sankaran Aniruddhan, "A Modified Bias Scheme for High-Gain Low-Noise Folded Cascode OTAs", //2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)//, Hsinchu, 2017, pp. 1-4. [[https://ieeexplore.ieee.org/document/8126531|doi: 10.1109/EDSSC.2017.8126531]] |
| - | * Ramakrishna Avula and Sankaran Aniruddhan, "Low-Voltage 0.5.3GHz Radio Receiver for Multiband Cellular Applications",// IEEE Electron Devices and Solid-State Circuits Conference (EDSSC 2017), October 2017//Hsinchu, Taiwan. | + | * Ramakrishna Avula and Sankaran Aniruddhan, "Low-Voltage 0.5.3GHz Radio Receiver for Multiband Cellular Applications," //2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)//, Hsinchu, 2017, pp. 1-2. [[https://ieeexplore.ieee.org/document/8126519|doi: 10.1109/EDSSC.2017.8126519]] |
| - | * Arpan Thakkar, Apoorva Bhatia, Vikram Sharma, Srinivas Theertham and Sankaran Aniruddhan, "A 4-Port Inductor based Compact Dual-core VCO with Improved Phase Noise Performance",// IEEE Electron Devices and Solid-State Circuits Conference (EDSSC 2017), October 2017//Hsinchu, Taiwan. | + | * Arpan Thakkar, Apoorva Bhatia, Vikram Sharma, Srinivas Theertham and Sankaran Aniruddhan, "A 4-Port Inductor based Compact Dual-core VCO with Improved Phase Noise Performance," //2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)//, Hsinchu, 2017, pp. 1-4. [[https://ieeexplore.ieee.org/document/8126521|doi: 10.1109/EDSSC.2017.8126521]] |
| - | * Arpan Thakkar, Srinivas Theertham, Sankaran Aniruddhan, Peeyoosh Mirajkar and Jagdish Chand Goyal, "A 3.9 - 4.5GHz Class-C VCO with Accurate Current Injection Based on Capacitive Feedback,"// European Microwave Integrated Circuits Conference (EuMIC), October 2017//Nuremberg, Germany. | + | * Arpan Thakkar, Srinivas Theertham, Sankaran Aniruddhan, Peeyoosh Mirajkar and Jagdish Chand Goyal, "A 3.9–4.5GHz class-C VCO with accurate current injection based on capacitive feedback," //2017 12th European Microwave Integrated Circuits Conference (EuMIC)//, Nuremberg, 2017, pp. 224-227. [[https://ieeexplore.ieee.org/document/8230700| doi: 10.23919/EuMIC.2017.8230700]] |
| - | * Sujith Billa, Amrith Sukumaran and Shanthi Pavan, "Analysis and Design of Continuous-time Delta-Sigma Modulators Incorporating Chopping,"//IEEE Journal of Solid State Circuits//, September 2017. | + | * Sujith Billa, Amrith Sukumaran and Shanthi Pavan, "Analysis and Design of Continuous-time Delta-Sigma Modulators Incorporating Chopping," //IEEE Journal of Solid-State Circuits//, vol. 52, no. 9, pp. 2350-2361, Sept. 2017. [[https://ieeexplore.ieee.org/document/7983340|doi: 10.1109/JSSC.2017.2717937]] |
| - | * Shanthi Pavan and Eric Klumperink,"Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network,"//IEEE Transactions on Circuits and Systems: Regular Papers//, October 2017. | + | * Shanthi Pavan and Eric Klumperink,"Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and $N$-Path Filters Using the Adjoint Network," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 64, no. 10, pp. 2714-2725, Oct. 2017. [[https://ieeexplore.ieee.org/document/7936531|doi: 10.1109/TCSI.2017.2703579]] |
| - | * Neha Sinha, Mansour Rachid, Shanthi Pavan and Sudhakar Pamarti,"Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With>+ 31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components," //IEEE Journal of Solid State Circuits//, August 2017. | + | * Neha Sinha, Mansour Rachid, Shanthi Pavan and Sudhakar Pamarti,"Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components," //IEEE Journal of Solid-State Circuits//, vol. 52, no. 8, pp. 2009-2025, Aug. 2017. [[https://ieeexplore.ieee.org/document/7932619|doi: 10.1109/JSSC.2017.2697412]] |
| - | * Shanthi Pavan, "Analysis of chopped integrators and its application to continuous-time delta-sigma modulator design,"//IEEE Transactions on Circuits and Systems: Regular Papers//, August 2017. | + | * Shanthi Pavan, "Analysis of chopped integrators and its application to continuous-time delta-sigma modulator design," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 64, no. 8, pp. 1953-1965, Aug. 2017. [[https://ieeexplore.ieee.org/document/7892869|doi: 10.1109/TCSI.2017.2682884]] |
| - | * Saravanan K. and S. Aniruddhan, "Area Efficient Low Power Crystal Oscillator with Automatic Amplitude Control,"// IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), August 2017//Boston, MA, USA. | + | * Saravanan K. and S. Aniruddhan, "Area Efficient Low Power Crystal Oscillator with Automatic Amplitude Control," //2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)//, Boston, MA, 2017, pp. 731-734. [[https://ieeexplore.ieee.org/document/8053027|doi: 10.1109/MWSCAS.2017.8053027]] |
| - | * Arjun Nadh, Joseph Samuel, Ankit Sharma, Sankaran Aniruddhan, and Radha Krishna Ganti, "A Taylor Series Approximation of Self-Interference Channel in Full-Duplex Radios,"//IEEE Transactions on Wireless Communications//, vol. 16, no.7, July 2017. | + | * Arjun Nadh, Joseph Samuel, Ankit Sharma, Sankaran Aniruddhan, and Radha Krishna Ganti, "A Taylor Series Approximation of Self-Interference Channel in Full-Duplex Radios," //IEEE Transactions on Wireless Communications//, vol. 16, no. 7, pp. 4304-4316, July 2017. [[https://ieeexplore.ieee.org/document/7913706|doi: 10.1109/TWC.2017.2696938]] |
| - | * Imon Mondal and Nagendra Krishnapura, "A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 μm CMOS." //IEEE J. Solid State Circuits//, IEEE Early access([[http://ieeexplore.ieee.org/document/7935368/|paper]]) | + | * Imon Mondal and Nagendra Krishnapura, "A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS," //IEEE Journal of Solid-State Circuits//, vol. 52, no. 8, pp. 2180-2193, Aug. 2017. [[https://ieeexplore.ieee.org/document/7935368|doi: 10.1109/JSSC.2017.2693229]] |
| - | * Sumit Kumar and Nagendra Krishnapura, "Optimum Scaling of Stages in a Frequency Divider Chain for Best Jitter FoM", //Proc. 2017 IEEE ISCAS//, Baltimore, USA, May 2017. | + | * Sumit Kumar and Nagendra Krishnapura, "Optimum Scaling of Stages in a Frequency Divider Chain for Best Jitter FoM," //2017 IEEE International Symposium on Circuits and Systems (ISCAS)//, Baltimore, MD, 2017, pp. 1-4. [[https://ieeexplore.ieee.org/document/8051001|doi: 10.1109/ISCAS.2017.8051001]] |
| - | * Shanthi Pavan, " On Linear Periodically Time Varying (LPTV) Systems with Modulated Inputs, and Their Application to Smoothing Filters", //Proc. 2017 IEEE ISCAS//, Baltimore, USA, May 2017. | + | * Shanthi Pavan, "On linear periodically time varying (LPTV) systems with modulated inputs, and their application to smoothing filters," //2017 IEEE International Symposium on Circuits and Systems (ISCAS)//, Baltimore, MD, 2017, pp. 1-4. [[https://ieeexplore.ieee.org/document/8050952|doi: 10.1109/ISCAS.2017.8050952]] |
| - | * Vinodhini G., Sankaran Aniruddhan, Boby George, Dhurga Devi J. and Ramakrishna P.V., "A Simple and Efficient Oscillator Based Read-out Scheme for LVDT,"// IEEE Instrumentation and Measurement Technology Conference (I2MTC), May 2017//Torino, Italy. | + | * Vinodhini G., Sankaran Aniruddhan, Boby George, Dhurga Devi J. and Ramakrishna P.V., "A Simple and Efficient Oscillator Based Read-out Scheme for LVDT,"// 2017 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)//, Turin, 2017, pp. 1-5. [[https://ieeexplore.ieee.org/document/7969655|doi: 10.1109/I2MTC.2017.7969655]] |
| - | * Sreenivasa Mallia S, Sreeram NS, Sudhir Adinarayana, and Sankaran Aniruddhan, "A Self-Powered 50Mbps OOK Transmitter for Opto-Isolator LED Emulation,"//IEEE Journal of Solid-State Circuits//, vol. 52, no. 3, March 2017. | + | * Sreenivasa Mallia S, Sreeram NS, Sudhir Adinarayana, and Sankaran Aniruddhan, "A Self-Powered 50-Mb/s OOK Transmitter for Optoisolator LED Emulation," //IEEE Journal of Solid-State Circuits//, vol. 52, no. 3, pp. 678-687, March 2017. [[https://ieeexplore.ieee.org/document/7852518|doi: 10.1109/JSSC.2016.2633577]] |
| - | * Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura, " A 500Mb/s, 200pJ/bit die-to-die bidirectional link with 24kV surge isolation and 50kV/s CMR using resonant inductive coupling in 180nm CMOS," //2017 International Solid-State Circuits Conference//, San Francisco, USA, Feb. 2017. | + | * Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura, "25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS," //2017 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2017, pp. 434-435. [[https://ieeexplore.ieee.org/document/7870447|doi: 10.1109/ISSCC.2017.7870447]] |
| - | * R. S. Ashwin Kumar and Nagendra Krishnapura, "A Low Power Multi-Channel Input Delta-Sigma ADC Without Reset," //30th International Conference on VLSI Design//, Hyderabad, India, Jan. 2017. | + | * R. S. Ashwin Kumar and Nagendra Krishnapura, "A Low Power Multi-channel Input Delta-Sigma ADC without Reset," //2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)//, Hyderabad, 2017, pp. 9-14. [[https://ieeexplore.ieee.org/document/7884750|doi: 10.1109/VLSID.2017.85]] |
| ===== 2016 ===== | ===== 2016 ===== | ||
| - | * Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti, "An Asymmetric 2.4 GHz Directional Coupler using Electrical Balance," //IEEE Microwave and Wireless Component Letters//, vol. 26, no. 12, December 2016. | + | * Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti, "An Asymmetric 2.4 GHz Directional Coupler Using Electrical Balance," //IEEE Microwave and Wireless Components Letters//, vol. 26, no. 12, pp. 990-992, Dec. 2016. [[https://ieeexplore.ieee.org/document/7737030|doi: 10.1109/LMWC.2016.2623252]] |
| - | * Gaurav Agrawal, Sankaran Aniruddhan, and Radha Krishna Ganti, "A Compact Mixer-First Receiver with >24dB Self-Interference Cancellation for Full-Duplex Radios," //IEEE Microwave and Wireless Component Letters//, vol. 26, no. 12, December 2016. | + | * Gaurav Agrawal, Sankaran Aniruddhan, and Radha Krishna Ganti, "A Compact Mixer-First Receiver With >24 dB Self-Interference Cancellation for Full-Duplex Radios," //IEEE Microwave and Wireless Components Letters//, vol. 26, no. 12, pp. 1005-1007, Dec. 2016. [[https://ieeexplore.ieee.org/document/7740043|doi: 10.1109/LMWC.2016.2623253]] |
| - | * Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar Khan, Toshiaki Kirihata, Subramanian S. Iyer: A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. J. Solid-State Circuits 51(1): 230-239 (2016) | + | * Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar Khan, Toshiaki Kirihata and Subramanian S. Iyer, "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," //IEEE Journal of Solid-State Circuits//, vol. 51, no. 1, pp. 230-239, Jan. 2016. [[https://ieeexplore.ieee.org/document/7210238|doi: 10.1109/JSSC.2015.2456873]] |
| - | * Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer: 80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits 2016: 1-2 | + | * Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer, "80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity," //2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)//, Honolulu, HI, 2016, pp. 1-2. [[https://ieeexplore.ieee.org/document/7573462|doi: 10.1109/VLSIC.2016.7573462]] |
| - | * Rakshitdatta K. S., Yujendra Mitikiri, and Nagendra Krishnapura, "A 12.5 mW, 11.1 nV/rtHz, −115dB THD, < 1 µs Settling, 18 bit SAR ADC Driver in 0.6µm CMOS," //IEEE Transactions on Circuits and Systems II-Express Briefs//, vol. 63, no. 5, pp. 443-447, May 2016. | + | * Rakshitdatta K. S., Yujendra Mitikiri, and Nagendra Krishnapura, "A 12.5 mW, 11.1 $\text{nV}/\sqrt{\text{Hz}}$, −115 dB THD, $ < 1\ \mu\text{s}$ Settling, 18 bit SAR ADC Driver in 0.6 $\mu\text{m}$ CMOS," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 63, no. 5, pp. 443-447, May 2016. [[https://ieeexplore.ieee.org/document/7337410|doi: 10.1109/TCSII.2015.2504024]] |
| - | * Abhishek Bhat and Nagendra Krishnapura, "A Tail-Resonance Calibration Technique for Wide Tuning Range LC VCOs", //Proc. 2016 ISCAS//, Montreal, May 2016. | + | * Abhishek Bhat and Nagendra Krishnapura, "A Tail-Resonance Calibration Technique for Wide Tuning Range LC VCOs," //2016 IEEE International Symposium on Circuits and Systems (ISCAS)//, Montreal, QC, 2016, pp. 2070-2073. [[https://ieeexplore.ieee.org/document/7538986|doi: 10.1109/ISCAS.2016.7538986]] |
| - | * Shanthi Pavan, "Continuous-Time Delta Sigma Modulators with Dual Switched Capacitor Resistor DACs", //Proc. 2016 ISCAS//, Montreal, May 2016. | + | * Shanthi Pavan, "Continuous-Time Delta Sigma Modulators with Dual Switched Capacitor Resistor DACs," //2016 IEEE International Symposium on Circuits and Systems (ISCAS)//, Montreal, QC, 2016, pp. 69-72. [[https://ieeexplore.ieee.org/document/7527172|doi: 10.1109/ISCAS.2016.7527172]] |
| - | * Aparna Girija and Aniruddhan S., "A Compact Dual-Band 5dBm RF Power Amplifier for Cellular Applications", //Proc. 2016 ISCAS//, Montreal, May 2016. | + | * Aparna Girija and Aniruddhan S, "A Compact Dual-Band 5dBm RF Power Amplifier for Cellular Applications," //2016 IEEE International Symposium on Circuits and Systems (ISCAS)//, Montreal, QC, 2016, pp. 2118-2121. [[https://ieeexplore.ieee.org/document/7538998|doi: 10.1109/ISCAS.2016.7538998]] |
| - | * A. Sukumaran and S. Pavan, "Design of Continuous-time Delta Sigma Modulators with Dual Switch Capacitor Return-to-Zero DACs" //IEEE Journal of Solid State Circuits//, July 2016. | + | * A. Sukumaran and S. Pavan, "Design of Continuous-Time $\Delta \Sigma $ Modulators With Dual Switched-Capacitor Return-to-Zero DACs," //IEEE Journal of Solid-State Circuits//, vol. 51, no. 7, pp. 1619-1629, July 2016. [[https://ieeexplore.ieee.org/document/7460888|doi: 10.1109/JSSC.2016.2542200]] |
| - | * A. Jain and S. Pavan, " A 13.3mW 60MHz Bandwidth, 76dB DR 6GS/s CTDSM with Time Interleaved FIR Feedback" // Symposium on VLSI Circuits , Honolulu, Hawaii//, June 2016 (to appear). | + | * A. Jain and S. Pavan, "A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback," //2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)//, Honolulu, HI, 2016, pp. 1-2. [[https://ieeexplore.ieee.org/document/7573466|doi: 10.1109/VLSIC.2016.7573466]] |
| - | * S. Pavan and R. Rajan, " Design Considerations for Filtering Delta Sigma Converters ", //Proceedings of the Workshop on Advanced Analog Circuit Design//, 24th-27th April 2016, Villach, Austria. | + | * S. Pavan and R. Rajan, "Design Considerations for Filtering Delta Sigma Converters", //Proceedings of the Workshop on Advanced Analog Circuit Design//, 24th-27th April 2016, Villach, Austria. [[https://doi.org/10.1007/978-3-319-41670-0_4]] |
| - | * S. Billa, A. Sukumaran and S. Pavan, "A 280uW, 24kHz BW, 98.5 dB SNDR, chopped single-bit CTDSM achieving < 10\,Hz 1/f noise corner without chopping artifacts " //International Solid State Circuits Conference//, 1st-4th February 2016, San Francisco, USA. | + | * S. Billa, A. Sukumaran and S. Pavan, "15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts," //2016 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2016, pp. 276-277. [[https://ieeexplore.ieee.org/document/7418014|doi: 10.1109/ISSCC.2016.7418014]] |
| - | * K. Singh and S. Pavan, " A 14 bit Dual Channel Incremental Continuous-time Delta Sigma Modulator for Multiplexed Data Acquisition" //29th International Conference on VLSI Design//, 4-8 January 2016, Kolkata, India. | + | * K. Singh and S. Pavan, "A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition," //2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)//, Kolkata, 2016, pp. 230-235. [[https://ieeexplore.ieee.org/document/7434957|doi: 10.1109/VLSID.2016.21]] |
| - | * S. Pavan and N. Krishnapura, "Demystifying Time-Varying Systems," //Half Day Tutorial at the 29th International Conference on VLSI Design//, 4-8 January 2016, Kolkata, India. | + | * S. Pavan and N. Krishnapura, "Demystifying Time Varying Circuits and Systems," //2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)//, Kolkata, 2016, pp. 17-18. [[https://ieeexplore.ieee.org/document/7434912|doi: 10.1109/VLSID.2016.135]] |
| - | * R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu,"A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC,"// IEEE Trans. Circuits Syst. I // (accepted). | + | * R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu, "A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 64, no. 2, pp. 283-295, Feb. 2017. [[https://ieeexplore.ieee.org/document/7731190|doi: 10.1109/TCSI.2016.2609855]] |
| - | * A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, "A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,"// IEEE J. Solid-State Circuits//, vol. 51, no. 8, pp. 1771-1784, Aug. 2016. | + | * A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, "A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider," //IEEE Journal of Solid-State Circuits//, vol. 51, no. 8, pp. 1771-1784, Aug. 2016. [[https://ieeexplore.ieee.org/document/7489022|doi: 10.1109/JSSC.2016.2557807]] |
| - | * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, "A 4-to-10.5-Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition," //IEEE J. Solid-State Circuits//, vol. 51, no. 2, pp. 428-439, Feb. 2016. | + | * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, "A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition," //IEEE Journal of Solid-State Circuits//, vol. 51, no. 2, pp. 428-439, Feb. 2016. [[https://ieeexplore.ieee.org/document/7362125|doi: 10.1109/JSSC.2015.2497963]] |
| - | * G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar, R. Nandwana, and P. K. Hanumolu,"A 16Mb/s-8Gb/s, 14.1-7.2pJ/bit source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS," //ISSCC Digest of Technical Papers//, pp. 398-399, Feb. 2016. | + | * G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar, R. Nandwana, and P. K. Hanumolu, "23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS," //2016 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2016, pp. 398-399. [[https://ieeexplore.ieee.org/document/7418075|doi: 10.1109/ISSCC.2016.7418075]] |
| ===== 2015 ===== | ===== 2015 ===== | ||
| - | * J. d. l. Rosa, K. Pun, R. Schreier, and S. Pavan. Next-generation delta-sigma converters : Trends and perspectives. IEEE Journal of Emerging Topics in Circuits and Systems (JETCAS), 5(4):Dec, 2015. | + | * J. d. l. Rosa, K. Pun, R. Schreier, and S. Pavan, "Next-Generation Delta-Sigma Converters: Trends and Perspectives," //IEEE Journal on Emerging and Selected Topics in Circuits and Systems//, vol. 5, no. 4, pp. 484-499, Dec. 2015. [[https://ieeexplore.ieee.org/document/7343753|doi: 10.1109/JETCAS.2015.2502164]] |
| - | * Amrith Sukumaran and Shanthi Pavan, "A Continuous-Time Delta Sigma Modulator with 91 dB Dynamic Range in a 2MHz Signal Bandwidth Using a Dual Switched-Capacitor Return-to-Zero DAC," //2015 ESSCIRC//, Graz, Austria, Sep. 2015. | + | * Amrith Sukumaran and Shanthi Pavan, "A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC," //ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)//, Graz, 2015, pp. 217-220. [[https://ieeexplore.ieee.org/document/7313866|doi: 10.1109/ESSCIRC.2015.7313866]] |
| - | * Imon Mondal and Nagendra Krishnapura, "Gain enhanced high frequency OTA with on-chip tuned negative conductance load," //2015 IEEE ISCAS//, pp. 2085 - 2088, Lisbon, Portugal, May. 2015. | + | * Imon Mondal and Nagendra Krishnapura, "Gain enhanced high frequency OTA with on-chip tuned negative conductance load," //2015 IEEE International Symposium on Circuits and Systems (ISCAS)//, Lisbon, 2015, pp. 2085-2088. [[https://ieeexplore.ieee.org/document/7169089|doi: 10.1109/ISCAS.2015.7169089]] |
| - | * Sandeep Krishnan and Shanthi Pavan, "A 10 Gbps eye opening monitor in 65nm CMOS," //2015 IEEE ISCAS//, pp. 3028 - 3031, Lisbon, Portugal, May. 2015. | + | * Sandeep Krishnan and Shanthi Pavan, "A 10 Gbps eye opening monitor in 65nm CMOS," //2015 IEEE International Symposium on Circuits and Systems (ISCAS)//, Lisbon, 2015, pp. 3028-3031. [[https://ieeexplore.ieee.org/document/7169325|doi: 10.1109/ISCAS.2015.7169325]] |
| - | * Naga Rajesh and Shanthi Pavan, "Programmable analog pulse shaping for ultra-wideband applications," //2015 IEEE ISCAS//, pp. 461 - 464, Lisbon, Portugal, May. 2015. | + | * Naga Rajesh and Shanthi Pavan, "Programmable analog pulse shaping for ultra-wideband applications," //2015 IEEE International Symposium on Circuits and Systems (ISCAS)//, Lisbon, 2015, pp. 461-464. [[https://ieeexplore.ieee.org/document/7168670|doi: 10.1109/ISCAS.2015.7168670]] |
| - | * Rakshitdatta K. S. and Nagendra Krishnapura, "On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback," //28th International Conference on VLSI Design//, pp. 244-248, Bangalore, India, Jan. 2015. | + | * Rakshitdatta K. S. and Nagendra Krishnapura, "On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback," //2015 28th International Conference on VLSI Design//, Bangalore, 2015, pp. 244-248. [[https://ieeexplore.ieee.org/document/7031740|doi: 10.1109/VLSID.2015.47]] |
| - | * Imon Mondal and Nagendra Krishnapura, "Accurate Constant Transconductance Generation Without Off-chip Components," //28th International Conference on VLSI Design//, pp. 249-253, Bangalore, India, Jan. 2015. | + | * Imon Mondal and Nagendra Krishnapura, "Accurate Constant Transconductance Generation without Off-Chip Components," //2015 28th International Conference on VLSI Design//, Bangalore, 2015, pp. 249-253. [[https://ieeexplore.ieee.org/document/7031741|doi: 10.1109/VLSID.2015.48]] |
| - | * T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, "A 7Gb/s embedded clock transceiver for energy proportional links," //IEEE J. Solid-State Circuits//, vol. 50, no. 12, pp. 3101-3119, Dec. 2015. | + | * T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, "3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS," //2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers//, San Francisco, CA, 2015, pp. 1-3. [[https://ieeexplore.ieee.org/document/7062927|doi: 10.1109/ISSCC.2015.7062927]] |
| - | * R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, "A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method," //IEEE J. Solid-State Circuits//, vol. 50, no. 4, pp. 882-895, Apr. 2015. | + | * R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, "A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method," //IEEE Journal of Solid-State Circuits//, vol. 50, no. 4, pp. 882-895, April 2015. [[https://ieeexplore.ieee.org/document/7029717|doi: 10.1109/JSSC.2014.2385756]] |
| - | * A. Elkholy, S. Saxena, and P. K. Hanumolu, "A 4mW wide bandwidth ring-based fractional-N DPLL with 1.9psrms integrated-jitter," //IEEE Custom Int. Circuits Conf.//, pp. 1-4, Sept. 2015. | + | * A. Elkholy, S. Saxena, and P. K. Hanumolu, "A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter," //2015 IEEE Custom Integrated Circuits Conference (CICC)//, San Jose, CA, 2015, pp. 1-4. [[https://ieeexplore.ieee.org/document/7338376|doi: 10.1109/CICC.2015.7338376]] |
| - | * S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi, and P. K. Hanumolu, "A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS," //IEEE VLSI Circuits Sym. Tech. Papers //, pp. 1-2, June 2015. | + | * S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi and P. K. Hanumolu, "A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS," //2015 Symposium on VLSI Circuits (VLSI Circuits)//, Kyoto, 2015, pp. C352-C353. [[https://ieeexplore.ieee.org/document/7231320|doi: 10.1109/VLSIC.2015.7231320]] |
| - | * T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, "A 7Gb\/s rapid on/off embedded clock serial link transceiver with 20ns power-on time, 740uW off-state power for energy proportional links in 65nm CMOS," //ISSCC Digest of Technical Papers//, pp. 64-66, Feb. 2015. | + | * T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly and P. K. Hanumolu, "3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS," //2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers//, San Francisco, CA, 2015, pp. 1-3. [[https://ieeexplore.ieee.org/document/7062927|doi: 10.1109/ISSCC.2015.7062927]] |
| - | * S. J. Kim, R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski, and P. K. Hanumolu, “A 4-phase 30-70 MHz switching frequency buck converter using a time-based compensator,” IEEE J. Solid-State Circuits, vol.50, no.12, pp.2814-2824, Dec. 2015. | + | * S. J. Kim, R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski, and P. K. Hanumolu, “A 4-phase 30-70 MHz switching frequency buck converter using a time-based compensator,” //IEEE Journal of Solid-State Circuits//, vol. 50, no. 12, pp. 2814-2824, Dec. 2015. [[https://ieeexplore.ieee.org/document/7182789|doi: 10.1109/JSSC.2015.2456884]] |
| - | * S. J. Kim, Q. Khan, M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre, and P. K. Hanumolu, “High frequency buck converter design using time-based control techniques,” IEEE J. Solid-State Circuits,vol. 50, no. 4, pp. 990-1001, Apr. 2015. | + | * S. J. Kim, Q. Khan, M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre and P. K. Hanumolu, “High Frequency Buck Converter Design Using Time-Based Control Techniques," //IEEE Journal of Solid-State Circuits//, vol. 50, no. 4, pp. 990-1001, April 2015. [[https://ieeexplore.ieee.org/document/6998097|doi: 10.1109/JSSC.2014.2378216]] |
| - | * S. J. Kim; R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski, P. K. Hanumolu, “A 1.8V 30-to-70MHz 87% Peak Efficiency 0.32mm2 4-Phase Time-Based Buck Converter Consuming 3uA/MHz Quiescent Current in 65nm CMOS, ” 2015 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 22-26 Feb. 2015. | + | * S. J. Kim; R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski and P. K. Hanumolu, “12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS," //2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers//, San Francisco, CA, 2015, pp. 1-3. [[https://ieeexplore.ieee.org/document/7063003|doi: 10.1109/ISSCC.2015.7063003]] |
| ===== 2014 ===== | ===== 2014 ===== | ||
| - | * Debasish Behera and Nagendra Krishnapura, "A 2-Channel 1MHz BW, 80.5dB DR ADC Using ΔΣ Modulator and Zero-ISI Filter," //Proceedings of the 40th European Solid-State Circuits Conference//, Venice, Italy, Sep. 2014. | + | * Debasish Behera and Nagendra Krishnapura, "A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter," //ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)//, Venice Lido, 2014, pp. 415-418. [[https://ieeexplore.ieee.org/document/6942110|doi: 10.1109/ESSCIRC.2014.6942110]] |
| - | * R. Rajan and S.Pavan, "Design Techniques for Continuous-Time Delta Sigma ADCs with Embedded Active Filtering,"// IEEE Journal of Solid State Circuits,// to appear. | + | * R. Rajan and S.Pavan, "Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering," //IEEE Journal of Solid-State Circuits//, vol. 49, no. 10, pp. 2187-2198, Oct. 2014. [[https://ieeexplore.ieee.org/document/6880403|doi: 10.1109/JSSC.2014.2345023]] |
| - | * A. Sukumaran and S.Pavan, "Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback,"// IEEE Journal of Solid State Circuits,// Nov. 2014. | + | * A. Sukumaran and S.Pavan, "Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback," //IEEE Journal of Solid-State Circuits//, vol. 49, no. 11, pp. 2515-2525, Nov. 2014. [[https://ieeexplore.ieee.org/document/6862074|doi: 10.1109/JSSC.2014.2332885]] |
| - | * S.Pavan and R. Rajan," Simplified Analysis and Simulation of the STF, NTF and Noise in CTDSMs,"// IEEE Transactions on Circuits and Systems:Express Briefs,// September 2014. | + | * S.Pavan and R. Rajan, "Simplified Analysis and Simulation of the STF, NTF, and Noise in Continuous-Time $\Delta\Sigma$ Modulators," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 61, no. 9, pp. 681-685, Sept. 2014. [[https://ieeexplore.ieee.org/document/6848754|doi: 10.1109/TCSII.2014.2335414]] |
| - | * S.Pavan and R. Rajan," Interreciprocity in linear periodically time varying networks with sampled outputs,"// IEEE Transactions on Circuits and Systems:Express Briefs,// September 2014. | + | * S.Pavan and R. Rajan, "Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 61, no. 9, pp. 686-690, Sept. 2014. [[https://ieeexplore.ieee.org/document/6848783|doi: 10.1109/TCSII.2014.2335393]] |
| - | * Nagendra Krishnapura and K. S. Rakshitdatta, "A Model Agnostic Technique for Simulating Per-Element Distortion Contributions," //IEEE Transactions on Circuits and Systems I: Regular Papers//, Aug. 2014. | + | * Nagendra Krishnapura and K. S. Rakshitdatta, "A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 61, no. 8, pp. 2219-2228, Aug. 2014. [[https://ieeexplore.ieee.org/document/6848853|doi: 10.1109/TCSI.2014.2333681]] |
| - | * N. Rajesh and S.Pavan," Design of Lumped Component Programmable Delay Elements for Ultra-Wideband Beamforming,"// IEEE Journal of Solid State Circuits,// August 2014. | + | * N. Rajesh and S.Pavan, "Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming," //IEEE Journal of Solid-State Circuits//, vol. 49, no. 8, pp. 1800-1814, Aug. 2014. [[https://ieeexplore.ieee.org/document/6809227|doi: 10.1109/JSSC.2014.2317132]] |
| - | * Abhishek Kumar, S. Aniruddhan and Radha Krishna Ganti, "Directional Coupler with High Isolation Bandwidth using Electrical Balance," //2014 IEEE International Microwave Symposium//, Tampa Bay, Florida, USA, 01-06 June 2014. ([[http://www.ee.iitm.ac.in/~ani/papers/iitm-TLdir-coupler-IMS2014.pdf|paper]], [[http://www.ee.iitm.ac.in/~ani/papers/iitm-TLdir-coupler-IMS2014-slides.pdf|slides]]) | + | * Abhishek Kumar, S. Aniruddhan and Radha Krishna Ganti, "Directional coupler with high isolation bandwidth using electrical balance," //2014 IEEE MTT-S International Microwave Symposium (IMS2014)//, Tampa, FL, 2014, pp. 1-3. [[https://ieeexplore.ieee.org/document/6848434|doi: 10.1109/MWSYM.2014.6848434]] |
| - | * Saravanan K. and S. Aniruddhan, "Replica Bias Scheme for Efficient Power Utilization in High-Frequency CMOS Digital Circuits," //2014 International Symposium on Circuits and Systems (ISCAS)//, Melbourne, Australia, 01-05 June 2014. ([[http://www.ee.iitm.ac.in/~ani/papers/iitm-replica-bias-ISCAS2014.pdf|paper]], [[http://www.ee.iitm.ac.in/~ani/papers/iitm-replica-bias-ISCAS2014-slides.pdf|slides]]) | + | * Saravanan K and S. Aniruddhan, "Replica bias scheme for efficient power utilization in high-frequency CMOS digital circuits," //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 1002-1005. [[https://ieeexplore.ieee.org/document/6865307|doi: 10.1109/ISCAS.2014.6865307]] |
| - | * Abhishek Kumar and S. Aniruddhan, "Ground-Bounce Reduction in Narrow-Band RF Front-Ends," //2014 International Symposium on Circuits and Systems (ISCAS)//, Melbourne, Australia, 01-05 June 2014. ([[http://www.ee.iitm.ac.in/~ani/papers/iitm-gnd-bounce-ISCAS2014.pdf|paper]], [[http://www.ee.iitm.ac.in/~ani/papers/iitm-gnd-bounce-ISCAS2014-slides.pdf|slides]]) | + | * Abhishek Kumar and S. Aniruddhan, "Ground-Bounce Reduction in Narrow-Band RF Front-Ends," //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 189-192. [[https://ieeexplore.ieee.org/document/6865097|doi: 10.1109/ISCAS.2014.6865097]] |
| - | * Gaurav Agrawal, S. Aniruddhan and Radha Krishna Ganti, "Multi-Band RF Time Delay Element Based on Frequency Translation," //2014 International Symposium on Circuits and Systems (ISCAS)//, Melbourne, Australia, 01-05 June 2014. ([[http://www.ee.iitm.ac.in/~ani/papers/iitm-RF-delay-ISCAS2014.pdf|paper]], [[http://www.ee.iitm.ac.in/~ani/papers/iitm-RF-delay-ISCAS2014-poster.pdf|poster]]) | + | * Gaurav Agrawal, S. Aniruddhan and Radha Krishna Ganti, "Multi-band RF time delay element based on frequency translation," //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 1368-1371. [[https://ieeexplore.ieee.org/document/6865398|doi: 10.1109/ISCAS.2014.6865398]] |
| - | * S. Pavan, "Efficient estimation of Signal and Noise Transfer Functions in a Continuous-time Delta Sigma Modulator," // International Symposium on Circuits and Systems (ISCAS), // Melbourne, June 2014. | + | * S. Pavan, "Efficient estimation of noise and signal transfer functions of a continuous-time ΣΔ modulator," //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 726-729. [[https://ieeexplore.ieee.org/document/6865238|doi: 10.1109/ISCAS.2014.6865238]] |
| - | * S. Pavan, "Continuous time Delta Sigma Modulator Design using the Method of Moments," // IEEE Transactions on Circuits and Systems : Regular Papers, // June 2014. | + | * S. Pavan, "Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 61, no. 6, pp. 1629-1637, June 2014. [[https://ieeexplore.ieee.org/document/6728623|doi: 10.1109/TCSI.2013.2290846]] |
| - | * A. Jain and S. Pavan, " Characterization Techniques for High Speed Oversampled Data Converters," // IEEE Transactions on Circuits and Systems : Regular Papers, // May 2014. | + | * A. Jain and S. Pavan, "Characterization Techniques for High Speed Oversampled Data Converters," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 61, no. 5, pp. 1313-1320, May 2014. [[https://ieeexplore.ieee.org/document/6778807|doi: 10.1109/TCSI.2014.2309895]] |
| - | * Radha Rajan and S. Pavan, "A 5mW CT ΔΣ ADC with Embedded 2nd-Order Active Filter and VGA Achieving 82dB DR in 2MHz BW," // International Solid State Circuits Conference (ISSCC),// San Francisco, February 2014. | + | * R. Rajan and S. Pavan, "29.1 A 5mW CT ΔΣ ADC with embedded 2nd-order active filter and VGA achieving 82dB DR in 2MHz BW," //2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)//, San Francisco, CA, 2014, pp. 478-479. [[https://ieeexplore.ieee.org/document/6757520|doi: 10.1109/ISSCC.2014.6757520]] |
| - | * N. Krishnapura, "Pedagogy of Negative Feedback Circuits," //Half Day Tutorial at the 27th International Conference on VLSI Design//, 5-9 January 2014, Mumbai, India. | + | * N. Krishnapura, "Tutorial T6A: Pedagogy of Negative Feedback Circuits," //2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems//, Mumbai, 2014, pp. 13-13. [[https://ieeexplore.ieee.org/document/6733095|doi: 10.1109/VLSID.2014.121]] |
| - | * S. Saxena, R. K. Nandwana, and P. K. Hanumolu, "A 5Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis," //IEEE J. Solid-State Circuits//, vol. 49, no. 8, pp. 1827-1836, Aug. 2014. | + | * S. Saxena, R. K. Nandwana and P. K. Hanumolu, "A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis," //IEEE Journal of Solid-State Circuits//, vol. 49, no. 8, pp. 1827-1836, Aug. 2014. [[https://ieeexplore.ieee.org/document/6809856|doi: 10.1109/JSSC.2014.2317142]] |
| - | * G. Shu, S. Saxena, W. -S. Choi, M. Talegaonkar, A. Elshazly, B. Young, and P. K. Hanumolu, "A reference-less clock and data recovery circuit using phase-rotating phase-locked loop," //IEEE J. Solid-State Circuits//, vol. 49, no. 4, pp. 1036-1047, Apr. 2014. | + | * G. Shu, S. Saxena, W. -S. Choi, M. Talegaonkar, A. Elshazly, B. Young and P. K. Hanumolu, "A reference-less clock and data recovery circuit using phase-rotating phase-locked loop," //IEEE Journal of Solid-State Circuits//, vol. 49, no. 4, pp. 1036-1047, April 2014. [[https://ieeexplore.ieee.org/document/6712167|doi: 10.1109/JSSC.2013.2296152]] |
| - | * R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, "A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement,"// IEEE VLSI Circuits Sym. Tech. Papers//, pp. 1-2, June 2014. | + | * R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, "A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement," //2014 Symposium on VLSI Circuits Digest of Technical Papers//, Honolulu, HI, 2014, pp. 1-2. [[https://ieeexplore.ieee.org/document/6858446|doi: 10.1109/VLSIC.2014.6858446]] |
| - | * M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choi, and P. K. Hanumolu, "A 4.4-5.4GHz digital fractional-N pll using ΔΣ frequency-to-digital converter," //IEEE VLSI Circuits Sym. Tech. Papers//, pp. 1-2, June 2014. | + | * M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choi and P. K. Hanumolu, "A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter," //2014 Symposium on VLSI Circuits Digest of Technical Papers//, Honolulu, HI, 2014, pp. 1-2. [[https://ieeexplore.ieee.org/document/6858392|doi: 10.1109/VLSIC.2014.6858392]] |
| - | * A. Elkholy, A. Elshazly, S. Saxena, G. Shu, and P. K. Hanumolu, "A 20-to-1000MHz 14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS," //ISSCC Digest of Technical Papers//, pp. 272-273, Feb. 2014. | + | * A. Elkholy, A. Elshazly, S. Saxena, G. Shu and P. K. Hanumolu, "15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS," //2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)//, San Francisco, CA, 2014, pp. 272-273. [[https://ieeexplore.ieee.org/document/6757431|doi: 10.1109/ISSCC.2014.6757431]] |
| - | * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, "A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS,"// ISSCC Digest of Technical Papers//, pp. 150-151, Feb. 2014. | + | * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly and P. K. Hanumolu, "8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS," //2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)//, San Francisco, CA, 2014, pp. 150-151. [[https://ieeexplore.ieee.org/document/6757377|doi: 10.1109/ISSCC.2014.6757377]] |
| - | * Q. Khan, S. J. Kim; M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre and P. K. Hanumolu, “A 10-25MHz, 600mA buck converter using time-based PID compensator with 2uA/MHz quiescent current, 94% peak efficiency, and 1MHz BW,” VSLI Symp., June 2014, Honolulu. | + | * Q. Khan, S. J. Kim; M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre and P. K. Hanumolu, “A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW," //2014 Symposium on VLSI Circuits Digest of Technical Papers//, Honolulu, HI, 2014, pp. 1-2. [[https://ieeexplore.ieee.org/document/6858439|doi: 10.1109/VLSIC.2014.6858439]] |
| ===== 2013 ===== | ===== 2013 ===== | ||
| - | * Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction for Skewed Gaussian Variations. International Workshop on Physics of Semiconductor Devices 207-209 (December 2013) | + | * Janakiraman V., Pandharpure S.J. and Watts J., (2014) "Statistical Compact Model Extraction for Skewed Gaussian Variations", "In: Jain V., Verma A. (eds) Physics of Semiconductor Devices. Environmental Science and Engineering". Springer, Cham. [[https://link.springer.com/chapter/10.1007%2F978-3-319-03002-9_51|paper]] |
| - | * S. Pavan, "Systematic Derivation of Well Known Analog Circuits," // Tutorial at IEEE PRIME-Asia //, Vishakapatnam, Dec. 2013. | + | * S. Pavan, "Systematic Derivation of Well Known Analog Circuits," //2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)//, Visakhapatnam, 2013, pp. 1-12. [[https://ieeexplore.ieee.org/document/6731167|doi: 10.1109/PrimeAsia.2013.6731167]] |
| - | * M.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan, "Compact silicon biosensor for the clinical range estimation of blood serum triglyceride, " // Proceedings of the IEEE Sensors Conference, // Baltimore, Nov. 2013. | + | * M.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan, "Compact silicon biosensor for the clinical range estimation of blood serum triglycéride," //SENSORS, 2013 IEEE//, Baltimore, MD, 2013, pp. 1-4. [[https://ieeexplore.ieee.org/document/6688212|doi: 10.1109/ICSENS.2013.6688212]] |
| - | * A. Sukumaran and S. Pavan, "A 280 μW Audio Continuous-Time Modulator with 103 dB DR and 102 dB A-Weighted SNR," //Proceedings of the 2013 Asian Solid State Circuits Conference//, Singapore, Nov. 2013. | + | * A. Sukumaran and S. Pavan, "A 280 μW Audio Continuous-Time Modulator with 103 dB DR and 102 dB A-Weighted SNR," //2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)//, Singapore, 2013, pp. 385-388. [[https://ieeexplore.ieee.org/document/6691063|doi: 10.1109/ASSCC.2013.6691063]] |
| - | * A. Sukumaran, K. Karanjkar, S. Jhanwar, N. Krishnapura and S. Pavan, "A 1.2 V 285 μA Analog Front End Chip for a Digital Hearing Aid in 0.13μm CMOS," //Proceedings of the 2013 Asian Solid State Circuits Conference//, Singapore, Nov. 2013. | + | * A. Sukumaran, K. Karanjkar, S. Jhanwar, N. Krishnapura and S. Pavan, "A 1.2 V 285 μA Analog Front End Chip for a Digital Hearing Aid in 0.13μm CMOS," //2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)//, Singapore, 2013, pp. 397-400. [[https://ieeexplore.ieee.org/document/6691066|doi: 10.1109/ASSCC.2013.6691066]] |
| - | * N. Krishnapura and Rakshitdatta K. S., "A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions," //Proceedings of the 2013 IEEE Custom Integrated Circuits Conference//, September 2013. | + | * N. Krishnapura and Rakshitdatta K. S., "A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions," //Proceedings of the IEEE 2013 Custom Integrated Circuits Conference//, San Jose, CA, 2013, pp. 1-4. [[https://ieeexplore.ieee.org/document/6658427|doi: 10.1109/CICC.2013.6658427]] |
| - | * N. Rajesh and S. Pavan, "A Lumped Component Programmable Delay Element for Ultra-Wideband Beamforming," //Proceedings of the 2013 IEEE Custom Integrated Circuits Conference//, September 2013. | + | * N. Rajesh and S. Pavan, "A Lumped Component Programmable Delay Element for Ultra-Wideband Beamforming," //Proceedings of the IEEE 2013 Custom Integrated Circuits Conference//, San Jose, CA, 2013, pp. 1-4. [[https://ieeexplore.ieee.org/document/6658475|doi: 10.1109/CICC.2013.6658475]] |
| - | * T.Nandi, K.Boominathan and S.Pavan, "Continuous-time Delta Sigma Modulators with Enhanced Linearity and Reduced Clock Jitter Sensitivity using the Switched Capacitor Return to Zero DAC", // IEEE Journal of Solid State Circuits //, August 2013 (to appear). | + | * T.Nandi, K.Boominathan and S.Pavan, "Continuous-Time $\Delta \Sigma $ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC," //IEEE Journal of Solid-State Circuits//, vol. 48, no. 8, pp. 1795-1805, Aug. 2013. [[https://ieeexplore.ieee.org/document/6515127|doi: 10.1109/JSSC.2013.2259012]] |
| - | * M.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan, "A Miniaturized pH Sensor With an Embedded Counter Electrode and a Readout Circuit", // IEEE Sensors Journal //, May 2013. | + | * M.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan, "A Miniaturized pH Sensor With an Embedded Counter Electrode and a Readout Circuit", //IEEE Sensors Journal//, vol. 13, no. 5, pp. 1941-1948, May 2013. [[https://ieeexplore.ieee.org/document/6428589|doi: 10.1109/JSEN.2013.2245032]] |
| - | * A. Jain and S. Pavan, "Improved Characterization of High Speed Continuous-Time Delta Sigma Modulators Using a Duobinary Test Interface," // Proceedings of the International Symposium on Circuits and Systems (ISCAS)//, Beijing, May 2013 **(winner of the Best Student Paper Award at ISCAS 2013)**. | + | * A. Jain and S. Pavan, "Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface," //2013 IEEE International Symposium on Circuits and Systems (ISCAS)//, Beijing, 2013, pp. 1252-1255. [[https://ieeexplore.ieee.org/document/6572080|doi: 10.1109/ISCAS.2013.6572080]] |
| - | * S. Pavan, "A Time Domain Perspective of the Signal Transfer Function of a Continuous-time Delta Sigma Modulator," // IEEE Transactions on Circuits and Systems : Express Briefs //, February 2013. | + | * S. Pavan, "A Time Domain Perspective of the Signal Transfer Function of a Continuous-time Delta Sigma Modulator," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 60, no. 2, pp. 81-85, Feb. 2013 [[https://ieeexplore.ieee.org/document/6477097|doi: 10.1109/TCSII.2012.2235016]] |
| - | * S. Pavan, "Simulation Techniques in Data Converter Design," // Tutorial at the International Solid State Circuits Conference (ISSCC) //, February 2013. | + | * S. Pavan, "Simulation Techniques in Data Converter Design," //Tutorial at the International Solid State Circuits Conference (ISSCC)//, February 2013. [[https://resourcecenter.sscs.ieee.org/short-courses-and-tutorials/2013-isscc-short-courses-and-tutorials/SSCSTUT20130102.html|paper]] |
| - | * S. Saxena, R. K. Nandwana, and P. K. Hanumolu, "A 5Gb/s 3.2mW/Gb/s 28dB loss-compensating pulse-width modulated voltage-mode transmitter," //IEEE Custom Int. Circuits Conf.//, pp. 1-4, Sept. 2013. | + | * S. Saxena, R. K. Nandwana and P. K. Hanumolu, "A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter," //Proceedings of the IEEE 2013 Custom Integrated Circuits Conference//, San Jose, CA, 2013, pp. 1-4. [[https://ieeexplore.ieee.org/document/6658403|doi: 10.1109/CICC.2013.6658403]] |
| - | * R. K. Nandwana, S. Saxena, and P. K. Hanumolu, "A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC," //IEEE VLSI Circuits Sym. Tech. Papers//, pp. 156-157, June 2013. | + | * R. K. Nandwana, S. Saxena and P. K. Hanumolu, "A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC," //2013 Symposium on VLSI Circuits//, Kyoto, 2013, pp. C156-C157. [[https://ieeexplore.ieee.org/document/6578645|paper]] |
| - | * G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu,"A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR,"// IEEE VLSI Circuits Sym. Tech. Papers//, pp. 278-279, June 2013. | + | * G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu,"A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR," //2013 Symposium on VLSI Circuits//, Kyoto, 2013, pp. C278-C279. [[https://ieeexplore.ieee.org/document/6578694|paper]] |
| ===== 2012 ===== | ===== 2012 ===== | ||
| - | * Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction: A Neural Network Approach. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1920-1924 (2012) | + | * Janakiraman Viraraghavan, Shrinivas J. Pandharpure and Josef Watts, "Statistical Compact Model Extraction: A Neural Network Approach," //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems//, vol. 31, no. 12, pp. 1920-1924, Dec. 2012. [[https://ieeexplore.ieee.org/document/6349439|doi: 10.1109/TCAD.2012.2207955]] |
| - | * P. Shettigar and S.Pavan, "Design Techniques for Wideband Continuous-time Delta-Sigma Modulators with FIR Feedback DACs," // IEEE Journal of Solid State Circuits //, December 2012. | + | * P. Shettigar and S.Pavan, "Design Techniques for Wideband Continuous-time Delta-Sigma Modulators with FIR Feedback DACs," //IEEE Journal of Solid-State Circuits//, vol. 47, no. 12, pp. 2865-2879, Dec. 2012. [[https://ieeexplore.ieee.org/document/6341855|doi: 10.1109/JSSC.2012.2217871]] |
| - | * T. Nandi, K. Boominathan and S.Pavan, " A Continuous-time Delta Sigma Modulator with 87dB Dynamic Range in a 2MHz Signal Bandwidth Using a Switched-Capacitor Return-to-Zero DAC," //Proceedings of the 2012 Custom Integrated Circuits Conference (CICC) //, San Jose, California, 2012. | + | * T. Nandi, K. Boominathan and S.Pavan, " A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC," //Proceedings of the IEEE 2012 Custom Integrated Circuits Conference//, San Jose, CA, 2012, pp. 1-4. [[https://ieeexplore.ieee.org/document/6330692|doi: 10.1109/CICC.2012.6330692]] |
| - | * R.S.Rajan and S.Pavan, "Device Noise in continuous-time delta-sigma modulators," //IEEE Transactions on Circuits and Systems: Regular Papers //, September 2012. | + | * R.S.Rajan and S.Pavan, "Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs," //2012 IEEE International Symposium on Circuits and Systems (ISCAS)//, Seoul, 2012, pp. 524-527. [[https://ieeexplore.ieee.org/document/6272081|doi: 10.1109/ISCAS.2012.6272081]] |
| - | * V. Singh, N. Krishnapura, S.Pavan, B.Vigraham, D.Behera and N.Nigania "A 16 MHz BW 75 dB DR CT Delta Sigma ADC Compensated for More Than One Cycle Excess Loop Delay," //IEEE Journal of Solid State Circuits //,August 2012. | + | * V. Singh, N. Krishnapura, S.Pavan, B.Vigraham, D.Behera and N.Nigania "A 16 MHz BW 75 dB DR CT $\Delta\Sigma$ ADC Compensated for More Than One Cycle Excess Loop Delay," //IEEE Journal of Solid-State Circuits//, vol. 47, no. 8, pp. 1884-1895, Aug. 2012. [[https://ieeexplore.ieee.org/document/6220855|doi: 10.1109/JSSC.2012.2196730]] |
| - | * A.Jain, N. Muthusubramaniam and S.Pavan, "Analysis and Design of a High Speed Continuous Time Delta Sigma Modulator Using the Assisted Opamp Technique," //IEEE Journal of Solid State Circuits //, July 2012. | + | * A.Jain, N. Muthusubramaniam and S.Pavan, "Analysis and Design of a High Speed Continuous-time $\Delta\Sigma$ Modulator Using the Assisted Opamp Technique," //IEEE Journal of Solid-State Circuits//, vol. 47, no. 7, pp. 1615-1625, July 2012. [[https://ieeexplore.ieee.org/document/6190724|doi: 10.1109/JSSC.2012.2191210]] |
| - | * R.S.Rajan and S.Pavan, "Noise in CT DS Modulators with Switched Capacitor Feedback DACs," //Proceedings of the 2012 IEEE International Symposium on Circuits and Systems (ISCAS) //, Seoul, Korea, 2012. | + | * R.S.Rajan and S.Pavan, "Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs," //2012 IEEE International Symposium on Circuits and Systems (ISCAS)//, Seoul, 2012, pp. 524-527. [[https://ieeexplore.ieee.org/document/6272081/|doi: 10.1109/ISCAS.2012.6272081]] |
| - | * Nagendra Krishnapura, "Introducing Negative Feedback with an Integrator as the Central Element," //2012 International Symposium on Circuits and Systems (ISCAS)//, Seoul, South Korea, 20-23 May 2012. ([[http://www.ee.iitm.ac.in/~nagendra/papers/isc12-negfbwint-pap.pdf|paper]], [[http://www.ee.iitm.ac.in/~nagendra/papers/isc12-negfbwint-sl.pdf|slides]]) | + | * Nagendra Krishnapura, "Introducing negative feedback with an integrator as the central element," //2012 IEEE International Symposium on Circuits and Systems (ISCAS)//, Seoul, 2012, pp. 2449-2452. [[https://ieeexplore.ieee.org/document/6271794|doi: 10.1109/ISCAS.2012.6271794]] |
| - | * Nagendra Krishnapura, "Synthesis Based Introduction to Opamps and Phase Locked Loops," //2012 International Symposium on Circuits and Systems (ISCAS)//, Seoul, South Korea, 20-23 May 2012. ([[http://www.ee.iitm.ac.in/~nagendra/papers/isc12-opamppllsynth-pap.pdf|paper]], [[http://www.ee.iitm.ac.in/~nagendra/papers/isc12-opamppllsynth-sl.pdf|slides]]) | + | * Nagendra Krishnapura, "Synthesis based introduction to opamps and phase locked loops," //2012 IEEE International Symposium on Circuits and Systems (ISCAS)//, Seoul, 2012, pp. 2461-2464. [[https://ieeexplore.ieee.org/document/6271798|doi: 10.1109/ISCAS.2012.6271798]] |
| - | * Sankaran Aniruddhan, "Quadrature generation techniques in CMOS relaxation oscillators," //2012 International Symposium on Circuits and Systems (ISCAS)//, Seoul, South Korea, 20-23 May 2012. ([[http://www.ee.iitm.ac.in/~ani/papers/iitm-QRXO-ISCAS2012.pdf|paper]], [[http://www.ee.iitm.ac.in/~ani/papers/iitm-QRXO-ISCAS2012-slides.pdf|slides]]) | + | * Sankaran Aniruddhan, "Quadrature generation techniques in CMOS relaxation oscillators," //2012 IEEE International Symposium on Circuits and Systems (ISCAS)//, Seoul, 2012, pp. 1375-1378. [[https://ieeexplore.ieee.org/document/6271499|doi: 10.1109/ISCAS.2012.6271499]] |
| - | * P. Shettigar and S.Pavan, "A 15mW 3.6GS/s CT-Delta Sigma ADC with 36MHz Bandwidth and 83dB Dynamic Range in 90nm CMOS," //Proceedings of the 2012 IEEE International Solid State Circuits Conference (ISSCC) //, San Francisco, February 2012. **(Winner of the ISSCC 2012 Silk Road Award)** | + | * P. Shettigar and S.Pavan, "A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS," //2012 IEEE International Solid-State Circuits Conference//, San Francisco, CA, 2012, pp. 156-158. **(Winner of the ISSCC 2012 Silk Road Award)** [[https://ieeexplore.ieee.org/document/6176957|doi: 10.1109/ISSCC.2012.6176957]] |
| - | * R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, "A 75-dB SNDR, 5-MHz bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 16mW power," //IEEE Trans. Circuits Syst. I//, vol. 59, no. 8, pp. 1614-1625, Aug. 2012. | + | * R. Zanbaghi, S. Saxena, G. C. Temes and T. S. Fiez, "A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 59, no. 8, pp. 1614-1625, Aug. 2012. [[https://ieeexplore.ieee.org/abstract/document/6243236|doi: 10.1109/TCSI.2012.2206509]] |
| - | * S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, "A 12.5-bit 4MHz 13.8mW MASH ΔΣ modulator with multirated VCO-based ADC," //IEEE Trans. Circuits Syst. I//, vol. 59, no. 8, pp. 1604-1613, Aug. 2012. | + | * S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram and T. S. Fiez, "A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 59, no. 8, pp. 1604-1613, Aug. 2012. [[https://ieeexplore.ieee.org/abstract/document/6243235|doi: 10.1109/TCSI.2012.2206506]] |
| - | * Q. Khan, A. Elshazly, S. Rao,R. Inti and P. K. Hanumolu, “A 900mA 93% Efficient 50uA Quiescent Current Fixed Frequency Hysteretic Buck Converter Using a Highly Digital Hybrid Voltage- and Current-mode Control,” VSLI Symp., June 2012, Honolulu. | + | * Q. Khan, A. Elshazly, S. Rao,R. Inti and P. K. Hanumolu, “A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control," //2012 Symposium on VLSI Circuits (VLSIC)//, Honolulu, HI, 2012, pp. 182-183. [[https://ieeexplore.ieee.org/document/6243850|doi: 10.1109/VLSIC.2012.6243850]] |
| - | * | + | |
| ===== 2011 ===== | ===== 2011 ===== | ||
| - | * Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction: A Neural Network Approach, International Workshop on Physics of Semiconductor Devices, 2011 [**Poster**] | + | * Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts, "Statistical Compact Model Extraction: A Neural Network Approach, //International Workshop on Physics of Semiconductor Devices//, 2011 [**Poster**] [[https://aml.ece.iisc.ac.in/images/2/2c/Statistical-Modeling.pdf|poster]] |
| - | * Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera, "A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay," //Proceedings of the 2011 IEEE Custom Integrated Circuits Conference//, San Jose, September 2011. | + | * Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania and Debasish Behera, "A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay," //Proceedings of the 2011 IEEE Custom Integrated Circuits Conference//, San Jose, September 2011. [[https://ieeexplore.ieee.org/document/6220855|doi: 10.1109/JSSC.2012.2196730]] |
| - | * A. Jain, M. Venkatesan and S. Pavan, "A 4mW 1GS/S Continuous-Time DeltaSigma Modulator with 15.6MHz Bandwidth and 67dB Dynamic Range" // Proceedings of the European Solid State Circuits Conference//, Helsinki, September 2011. | + | * A. Jain, M. Venkatesan and S. Pavan, "A 4mW 1GS/S Continuous-Time DeltaSigma Modulator with 15.6MHz Bandwidth and 67dB Dynamic Range" //2011 Proceedings of the ESSCIRC (ESSCIRC)//, Helsinki, 2011, pp. 259-262. [[https://ieeexplore.ieee.org/document/6044956|doi: 10.1109/ESSCIRC.2011.6044956]] |
| - | * S. Thyagarajan, S. Pavan and P. Sankar, "Active Filters using the Gm-Assisted OTA-RC Technique", // IEEE Journal of Solid State Circuits, // July 2011. [[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5765707|(paper)]] | + | * S. Thyagarajan, S. Pavan and P. Sankar, "Active-RC Filters Using the Gm-Assisted OTA-RC Technique," //IEEE Journal of Solid-State Circuits//, vol. 46, no. 7, pp. 1522-1533, July 2011. [[https://ieeexplore.ieee.org/document/5765707|doi: 10.1109/JSSC.2011.2143590]] |
| - | * Chembiyan Thambidurai and Nagendra Krishnapura, "On Pulse Position Modulation and its Application to PLLs for Spur Reduction", //IEEE Transactions on Circuits and Systems I-Regular Papers//, vol. 58, no. 7, pp. 1483-1496, July 2011. | + | * Chembiyan Thambidurai and Nagendra Krishnapura, "On Pulse Position Modulation and Its Application to PLLs for Spur Reduction," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 58, no. 7, pp. 1483-1496, July 2011. [[https://ieeexplore.ieee.org/document/5892914|doi: 10.1109/TCSI.2011.2157749]] |
| - | * S. Aniruddhan, Sudip Shekhar and David J. Allstot, "A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing", //IEEE Transactions on Circuits and Systems I-Regular Papers//, vol. 58, no. 5, pp. 860-867, May 2011.([[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5661878|paper]]) | + | * S. Aniruddhan, Sudip Shekhar and David J. Allstot, "A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing", //IEEE Transactions on Circuits and Systems I-Regular Papers//, vol. 58, no. 5, pp. 860-867, May 2011. [[https://ieeexplore.ieee.org/document/5661878|doi: 10.1109/TCSI.2010.2090565]] |
| - | * S. Pavan, "On Continuous-time Delta-Sigma Modulators with Return-to-Open DACs", // IEEE Transactions on Circuits and Systems : Express Briefs, May 2011.([[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5771064|paper]]) // | + | * S. Pavan, "On Continuous-Time $\Delta\Sigma$ Modulators With Return-to-Open DACs," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 58, no. 5, pp. 284-288, May 2011. [[https://ieeexplore.ieee.org/document/5771064|doi: 10.1109/TCSII.2011.2124930]] |
| - | * Nagendra Krishnapura, Abhishek Agrawal, and Sameer Singh, "A High IIP3 Third Order Elliptic Filter with Current Efficient Feedforward Compensated Opamps," //IEEE Transactions on Circuits and Systems II-Express Briefs//, vol. 58, no. 4, pp. 205-209, April 2011. ([[http://www.ee.iitm.ac.in/~nagendra/papers/tcas2-wlanfilter-pap.pdf|paper]]) | + | * Nagendra Krishnapura, Abhishek Agrawal and Sameer Singh, "A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 58, no. 4, pp. 205-209, April 2011. [[https://ieeexplore.ieee.org/document/5751658|doi: 10.1109/TCSII.2011.2124571]] |
| - | * Nagendra Krishnapura, "Electronic Time Stretching for Fast Digitization," //2011 International Symposium on Circuits and Systems (ISCAS)//, Rio de Janeiro, Brazil, 15-18 May 2011. | + | * Nagendra Krishnapura, "Electronic time stretching for fast digitization," //2011 IEEE International Symposium of Circuits and Systems (ISCAS)//, Rio de Janeiro, 2011, pp. 1391-1394. [[https://ieeexplore.ieee.org/document/5937832|doi: 10.1109/ISCAS.2011.5937832]] |
| - | * S. Pavan, "The Inconvenient Truth about Alias Rejection in Continuous-time Delta-Sigma Modulators", // Proceedings of the IEEE International Symposium on Circuits and Systems, // May 2011. | + | * S. Pavan, "The Inconvenient Truth about Alias Rejection in Continuous-time Delta-Sigma Modulators", //2011 IEEE International Symposium of Circuits and Systems (ISCAS)//, Rio de Janeiro, 2011, pp. 526-529. [[https://ieeexplore.ieee.org/document/5937618|doi: 10.1109/ISCAS.2011.5937618]] |
| - | * A. Cicalini, S. Aniruddhan, R. Apte, F. Bossu, O. Choksi, D. Filipovic, K. Godbole, T.P. Hung, C. Komninakis, D. Maldonado, C. Narathong, B. Nejati, D. O'Shea, X. Quan; R. Rangarajan, J. Sankaranarayanan, A. See, R. Sridhara, B. Sun; W. Su; K. van Zalinge, G. Zhang; K. Sahota, “A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor”, //Proceedings of the 2011 IEEE International Solid-State Circuits Conference//, San Francisco, February 2011. ([[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5746357|paper]]) | + | * A. Cicalini, S. Aniruddhan, R. Apte, F. Bossu, O. Choksi, D. Filipovic, K. Godbole, T.P. Hung, C. Komninakis, D. Maldonado, C. Narathong, B. Nejati, D. O'Shea, X. Quan, R. Rangarajan, J. Sankaranarayanan, A. See, R. Sridhara, B. Sun, W. Su, K. van Zalinge, G. Zhang and K. Sahota, “A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor," //2011 IEEE International Solid-State Circuits Conference//, San Francisco, CA, 2011, pp. 368-370. [[https://ieeexplore.ieee.org/document/5746357|doi: 10.1109/ISSCC.2011.5746357]] |
| - | * S. Pavan, "Alias Rejection of Continuous-time Delta-Sigma Converters with Switched-Capacitor Feedback DACs", // IEEE Transactions on Circuits and Systems : Regular Papers, // February 2011. [[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5641628|(paper)]] | + | * S. Pavan, "Alias Rejection of Continuous-Time $\Delta\Sigma$ Modulators With Switched-Capacitor Feedback DACs," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 58, no. 2, pp. 233-243, Feb. 2011. [[https://ieeexplore.ieee.org/abstract/document/5641628|doi: 10.1109/TCSI.2010.2071930]] |
| - | * R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, "A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW," //IEEE Custom Int. Circuits Conf.//, pp. 1-4, Sept. 2011. | + | * R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, "A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW," //2011 IEEE Custom Integrated Circuits Conference (CICC)//, San Jose, CA, 2011, pp. 1-4. [[https://ieeexplore.ieee.org/document/6055287|doi: 10.1109/CICC.2011.6055287]] |
| - | * S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, "A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer,"// IEEE Custom Int. Circuits Conf.//, pp. 1-4, Sept. 2011. | + | * S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, "A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer," //2011 IEEE Custom Integrated Circuits Conference (CICC)//, San Jose, CA, 2011, pp. 1-4. [[https://ieeexplore.ieee.org/document/6055290|doi: 10.1109/CICC.2011.6055290]] |
| - | * S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, P.K. Hanumolu, “A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique,” IEEE Journal of Solid-State Circuits, Volume: 46, Issue: 12, pp 2772- 2783, Dec. 2011. | + | * S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre and P.K. Hanumolu, “A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique,” //IEEE Journal of Solid-State Circuits//, Volume: 46, Issue: 12, pp 2772- 2783, Dec. 2011. [[https://ieeexplore.ieee.org/document/6007147|doi: 10.1109/JSSC.2011.2162921]] |
| - | * Q. Khan, S. Rao, D. Swank, A. Rao, W. McIntyre, S. Bang, P.K. Hanumolu, “A 3.3V 500mA Digital Buck-Boost Converter with 92% Peak Efficiency Using Constant ON/OFF Time Delta-Sigma Fractional-N Control,” 37th European Solid-State Circuits Conference (ESSCIRC), 12-16 Sept. 2011, Helsinki, Finland. | + | * Q. Khan, S. Rao, D. Swank, A. Rao, W. McIntyre, S. Bang and P.K. Hanumolu, "A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control," //2011 Proceedings of the ESSCIRC (ESSCIRC)//, Helsinki, 2011, pp. 439-442. [[https://ieeexplore.ieee.org/document/6045001|doi: 10.1109/ESSCIRC.2011.6045001]] |
| - | * S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, P.K. Hanumolu, “A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing,” 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 20-24 Feb. 2011. | + | * S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre and P.K. Hanumolu, “A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing," //2011 IEEE International Solid-State Circuits Conference//, San Francisco, CA, 2011, pp. 238-240. [[https://ieeexplore.ieee.org/document/5746300|doi: 10.1109/ISSCC.2011.5746300]] |
| ===== 2010 ===== | ===== 2010 ===== | ||
| - | * Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan: Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1056-1069 (2010) | + | * Janakiraman Viraraghavan, Bharadwaj Amrutur and V. Visvanathan, "Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks," //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems//, vol. 29, no. 7, pp. 1056-1069, July 2010. [[https://ieeexplore.ieee.org/abstract/document/5487472|doi: 10.1109/TCAD.2010.2049059]] |
| - | * S. Pavan, "High-Performance Continuous-time Delta Sigma Converters," Educational Sessions of the Custom Integrated Circuits Conference, San Jose, USA, 2010. | + | * S. Pavan, "Design Techniques for High-Performance Continuous-time Delta Sigma Conversion," //half day tutorial at the European Solid State Circuits Conference//, Seville, Spain, 2010. |
| - | * S. Pavan, ``Design Techniques for High-Performance Continuous-time Delta Sigma Conversion," half day tutorial at the European Solid State Circuits Conference, Seville, Spain, 2010. | + | * S. Thyagarajan, S. Pavan and P. Sankar, "Low distortion active filters using the Gm-assisted OTA-RC technique," //2010 Proceedings of ESSCIRC//, Seville, 2010, pp. 162-165. [[https://ieeexplore.ieee.org/document/5619904|doi: 10.1109/ESSCIRC.2010.5619904]] |
| - | * S. Thyagarajan, S. Pavan and P. Sankar, ``Low Distortion Active Filter Design using the Gm-Assisted OTA-RC Technique," // at the European Solid State Circuits Conference, Seville, Spain //, September 2010.([[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5619904|paper]]) | + | * V. Singh, N. Krishnapura and S. Pavan, "Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time $\Delta\Sigma$ Modulators," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 57, no. 9, pp. 676-680, Sept. 2010. [[https://ieeexplore.ieee.org/document/5570930|doi: 10.1109/TCSII.2010.2058496]] |
| - | * V. Singh, N. Krishnapura, S. Pavan, "Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time ΔΣ Modulators," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 57, no. 9, pp. 676-680, Sep. 2010. ([[http://www.ee.iitm.ac.in/~nagendra/papers/tcas2-eldcomp-pap.pdf|paper]]) | + | * S. Pavan, "Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 57, no. 8, pp. 1925-1934, Aug. 2010. [[https://ieeexplore.ieee.org/document/5416327|doi: 10.1109/TCSI.2009.2039833]] |
| - | * S. Pavan, "Efficient simulation of weak nonlinearities in continuous-time oversampling converters", // IEEE Transactions on Circuits and Systems : Regular Papers, // August 2010. [[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5416327|(paper)]] | + | * S. Pavan and P. Sankar, "Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique," //IEEE Journal of Solid-State Circuits//, vol. 45, no. 7, pp. 1365-1379, July 2010. [[https://ieeexplore.ieee.org/document/5492314|doi: 10.1109/JSSC.2010.2048082]] |
| - | * S. Pavan and P. Sankar, "Power reduction in continuous-time Delta-Sigma Modulators using the assisted opamp technique", // IEEE Journal of Solid State Circuits, // July 2010. [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5492314|(paper)]] **(most read paper in the IEEE Journal of Solid State Circuits in July 2010, and 11th most downloaded paper from ALL of IEEEXplore in July 2010)**{{publications:assisted_amp_top100.pdf|link}} | + | * N. Krishnapura, "Efficient determination of feedback DAC errors for digital correction in ΔΣ A/D converters," //Proceedings of 2010 IEEE International Symposium on Circuits and Systems//, Paris, 2010, pp. 301-304. [[https://ieeexplore.ieee.org/document/5537847|doi: 10.1109/ISCAS.2010.5537847]] |
| - | * N. Krishnapura, "Efficient Determination of Feedback Dac Errors for Digital Correction in Delta-Sigma A/D Converters," //2010 International Symposium on Circuits and Systems (ISCAS)//, Paris, France, 31 May-2 Jun. 2010. ([[href="http://www.ee.iitm.ac.in/~nagendra/papers/isc10-dsmdaccal-pap.pdf|paper]],[[href="http://www.ee.iitm.ac.in/~nagendra/papers/isc10-dsmdaccal-sl.pdf|slides]]) | + | * S. Parameswaran and N. Krishnapura, "A 100 µW Decimator for a 16 bit 24 kHz bandwidth Audio ΔΣ Modulator," //Proceedings of 2010 IEEE International Symposium on Circuits and Systems//, Paris, 2010, pp. 2410-2413. [[https://ieeexplore.ieee.org/document/5537170|doi: 10.1109/ISCAS.2010.5537170]] |
| - | * S. Parameswaran and N. Krishnapura, "A 100µW Decimator for a 16 Bit 24kHz Bandwidth Audio ΔΣ Modulator," //2010 International Symposium on Circuits and Systems (ISCAS)//, Paris, France, 31 May-2 Jun. 2010. ([[http://www.ee.iitm.ac.in/~nagendra/papers/isc10-decfil-pap.pdf|paper]], [[http://www.ee.iitm.ac.in/~nagendra/papers/isc10-decfil-sl.pdf|slides]]) | + | * C. Thambidurai and N. Krishnapura, "Spur reduction in wideband PLLs by random positioning of charge pump current pulses," //Proceedings of 2010 IEEE International Symposium on Circuits and Systems//, Paris, 2010, pp. 3397-3400. [[https://ieeexplore.ieee.org/document/5537876|doi: 10.1109/ISCAS.2010.5537876]] |
| - | * C. Thambidurai and N. Krishnapura, "Spur Reduction in Wideband PLLs by Random Positioning of Charge Pump Pulses," //2010 International Symposium on Circuits and Systems (ISCAS)//, Paris, France, 31 May-2 Jun. 2010. ([[http://www.ee.iitm.ac.in/~nagendra/papers/isc10-pllspurreduction-pap.pdf|paper]], [[http://www.ee.iitm.ac.in/~nagendra/papers/isc10-pllspurreduction-sl.pdf|slides]]) | + | * S. Pavan, "Understanding weak loop filter nonlinearities in continuous time ΔΣ converters," //Proceedings of 2010 IEEE International Symposium on Circuits and Systems//, Paris, 2010, pp. 17-20. [[https://ieeexplore.ieee.org/document/5537136|doi: 10.1109/ISCAS.2010.5537136]] |
| - | * S. Pavan, "Understanding weak nonlinearities in continuous-time oversampling converters", // IEEE International Symposium on Circuits and Systems (ISCAS), // Paris, May 2010. | + | * K. Reddy and S.Pavan, "A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range," //Analog Integr Circ Sig Process 63//, 397–406 (2010) [[https://link.springer.com/article/10.1007/s10470-009-9413-8|doi:10.1007/s10470-009-9413-8]] |
| - | * K. Reddy and S.Pavan, "A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range", // Analog Integrated Circuits and Signal Processing, // June 2010. [[http://www.springerlink.com/index/W73317501507760J.pdf|(paper)]] | + | * S. Pavan, "Systematic Design Centering of Continuous Time Oversampling Converters," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 57, no. 3, pp. 158-162, March 2010. [[https://ieeexplore.ieee.org/document/5437393|doi: 10.1109/TCSII.2010.2041814]] |
| - | * S. Pavan, "Systematic design centering of continuous-time oversampling converters", // IEEE Transactions on Circuits and Systems : Express Briefs, // March 2010 [[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5437393|(paper)]] | + | * S. Bang, D. Swank, A. Rao, W. McIntyre, Q. Khan and P.K. Hanumolu, "A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correction," //IEEE Custom Integrated Circuits Conference 2010//, San Jose, CA, 2010, pp. 1-4. [[https://ieeexplore.ieee.org/abstract/document/5617443|doi: 10.1109/CICC.2010.5617443]] |
| - | * S. Bang, D. Swank, A. Rao, W. McIntyre, Q. Khan, P.K. Hanumolu, “A 1.2A 2MHz Tri-Mode Buck-Boost LED Driver With Feed-Forward Duty Cycle Correction,” IEEE Custom Integrated Circuit Conference (CICC-2010), San Jose, California. September 2010. | + | * K. Jayaraman, Q. Khan, B. Chi, W. Beattie, Z. Wang and P. Chiang, "A self-healing 2.4GHz LNA with on-chip S11/S21 measurement/calibration for in-situ PVT compensation," //2010 IEEE Radio Frequency Integrated Circuits Symposium//, Anaheim, CA, 2010, pp. 311-314. [[https://ieeexplore.ieee.org/document/5477307|doi: 10.1109/RFIC.2010.5477307]] |
| - | * K. Jayaraman, Q. Khan, B. Chi, W. Beattie, Z. Wang, P. Chiang, “A Self-Healing 2.4GHz LNA with On-Chip S11S21 MeasurementCalibration for In-Situ PVT Compensation,” Radio Frequency Integrated Circuits (RFIC) Symposium, Anaheim, CA, May 2010. | + | |
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| ===== 2009 ===== | ===== 2009 ===== | ||
| - | * S.Pavan and P.Sankar, "A 110-microwatt Single Bit Audio Continuous-time Oversampled Converter with 92.5 dB Dynamic Range", // European Solid State Circuits Conference (ESSCIRC), // Athens, Greece, September 2009 ([[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325953&isnumber=5325915|paper]]). | + | * S.Pavan and P.Sankar, "A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range," //2009 Proceedings of ESSCIRC//, Athens, 2009, pp. 320-323. [[https://ieeexplore.ieee.org/document/5325953|doi: 10.1109/ESSCIRC.2009.5325953]] |
| - | * Y.Darhwekar, R.Kumar, D.Sahu, S.Pavan, A.Lacchwani and S.Mukherjee, "A Digitally Assisted Baseband Filter with 9 MHz Bandwidth and 0.3 dB IQ Mismatch for a WLAN Receiver Chain", //International Symposium on Circuits and Systems (ISCAS),// Taipei, Taiwan, 24-27 May 2009.[[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5117735|(paper)]] | + | * Y.Darhwekar, R.Kumar, D.Sahu, S.Pavan, A.Lacchwani and S.Mukherjee, "A digitally assisted baseband filter with 9MHz bandwidth and 0.3 dB IQ mismatch for a WLAN receiver chain," //2009 IEEE International Symposium on Circuits and Systems (ISCAS)//, Taipei, 2009, pp. 261-264. [[https://ieeexplore.ieee.org/document/5117735|doi: 10.1109/ISCAS.2009.5117735]] |
| - | * S.Saxena,P.Sankar and S.Pavan, "Automatic Tuning of Time Constants in Single-bit Continuous-time Delta Sigma Modulators",//International Symposium on Circuits and Systems (ISCAS),// Taipei, Taiwan, 24-27 May 2009. [[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5118248|(paper)]] | + | * S.Saxena,P.Sankar and S.Pavan, "Automatic tuning of time constants in single bit continuous-time delta-sigma modulators," //2009 IEEE International Symposium on Circuits and Systems//, Taipei, 2009, pp. 2257-2260. [[https://ieeexplore.ieee.org/document/5118248|doi: 10.1109/ISCAS.2009.5118248]] |
| - | * N.Krishnapura, V.Gupta, and N.Agrawal, "Compact Lowpass Ladder Filters Using Tapped Coils," //International Symposium on Circuits and Systems (ISCAS)//, Taipei, Taiwan, 24-27 May 2009. ([[http://www.ee.iitm.ac.in/~nagendra/papers/isc09-tappedlcfil-pap.pdf|paper]], [[http://www.ee.iitm.ac.in/~nagendra/papers/isc09-tappedlcfil-sl.pdf|slides]]) | + | * N.Krishnapura, V.Gupta and N.Agrawal, "Compact lowpass ladder filters using tapped coils," //2009 IEEE International Symposium on Circuits and Systems//, Taipei, 2009, pp. 53-56.) [[https://ieeexplore.ieee.org/document/5117683|doi: 10.1109/ISCAS.2009.5117683]] |
| - | * V. Vasudevan, "Analysis of Clock Jitter in Continuous-Time Sigma–Delta Modulators,", //IEEE Transactions on Circuits and Systems I : Regular Papers//, March 2009. ([[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4663683|paper]]) | + | * V. Vasudevan, "Analysis of clock jitter in continuous-time quadrature bandpass sigma-delta modulators with NRZ pulses," //2009 Ph.D. Research in Microelectronics and Electronics//, Cork, 2009, pp. 176-179. [[https://ieeexplore.ieee.org/document/5201334|doi: 10.1109/RME.2009.5201334]] |
| - | * T.Laxminidhi,V.Prasadu and S.Pavan, "Widely Programmable High Frequency Active-RC Filters in CMOS Technology", // IEEE Transactions on Circuits and Systems I : Regular Papers,//[[http://ieeexplore.ieee.org/iel5/8919/4358591/04571106.pdf?tp=&arnumber=4571106&isnumber=4358591|(paper)]] February 2009. | + | * T.Laxminidhi, V.Prasadu and S.Pavan, "Widely Programmable High-Frequency Active RC Filters in CMOS Technology," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 56, no. 2, pp. 327-336, Feb. 2009.. [[https://ieeexplore.ieee.org/document/4571106|doi: 10.1109/TCSI.2008.2001759]] |
| - | * L.Manojkumar,A.Mohan,N.Krishnapura, "A Comparison of Approaches to Carrier Generation in Zigbee Transceivers", //22nd International Conference on VLSI Design,// New Delhi, India, 5-9 Jan 2009.([[http://www.ee.iitm.ac.in/~nagendra/papers/vlsiconf2009_zigbeevco-pap.pdf|paper]], [[http://www.ee.iitm.ac.in/~nagendra/papers/vlsiconf2009_zigbeevco-sl.pdf|slides]]) | + | * L.Manojkumar, A.Mohan and N.Krishnapura, "A Comparison of Approaches to Carrier Generation for Zigbee Transceivers," //2009 22nd International Conference on VLSI Design//, New Delhi, 2009, pp. 367-372. [[https://ieeexplore.ieee.org/document/4749701|doi: 10.1109/VLSI.Design.2009.50]] |
| - | * N.Krishnapura and S.Pavan, "Negative Feedback System and Circuit Design", Full Day Tutorial at the International Conference on VLSI Design, 5-9 January 2009, New Delhi, India. ([[http://www.ee.iitm.ac.in/~nagendra/videolectures/doku.php?id=200901vlsiconf:start|Lecture and notes]]) | + | * N.Krishnapura and S.Pavan, "Negative Feedback System and Circuit Design," //2009 22nd International Conference on VLSI Design//, New Delhi, 2009, pp. 35-36. [[https://ieeexplore.ieee.org/document/4749647|doi: 10.1109/VLSI.Design.2009.116]] |
| ===== 2008 ===== | ===== 2008 ===== | ||
| - | * Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan: Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. J. Low Power Electronics 4(3): 301-319 (2008) | + | * Janakiraman Viraraghavan, Bharadwaj Amrutur and V. Visvanathan, "Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks," //Journal of Low Power Electronics//, Volume 4, Number 3, December 2008, pp. 301-319(19) [[https://www.ingentaconnect.com/content/asp/jolpe/2008/00000004/00000003/art00005;jsessionid=9mno0749sse6r.x-ic-live-03|doi:10.1166/jolpe.2008.187]] |
| - | * Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur: Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. VLSI Design 2008: 667-672 | + | * Janakiraman Viraraghavan, Bishnu Prasad Das and Bharadwaj Amrutur, "Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization," //21st International Conference on VLSI Design (VLSID 2008)//, Hyderabad, 2008, pp. 667-672. [[https://ieeexplore.ieee.org/document/4450574|doi: 10.1109/VLSI.2008.38]] |
| - | * Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind: Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. VLSI Design 2008: 685-691 | + | * Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni and N. V. Arvind, "Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations," //21st International Conference on VLSI Design (VLSID 2008)//, Hyderabad, 2008, pp. 685-691. [[https://ieeexplore.ieee.org/document/4450577|doi: 10.1109/VLSI.2008.92]] |
| - | * V.Hareesh, S.Pavan and E.Bhattacharya, "Readout Circuit Design for an EISCAP Biosensor", // IEEE Biomedical Circuits and Systems Conference,// November 2008.[[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4696877&isnumber=4696849|(paper)]] | + | * V.Hareesh, S.Pavan and E.Bhattacharya, "Readout circuit design for an EISCAP biosensor," //2008 IEEE Biomedical Circuits and Systems Conference//, Baltimore, MD, 2008, pp. 73-76. [[https://ieeexplore.ieee.org/document/4696877|doi: 10.1109/BIOCAS.2008.4696877]] |
| - | * S.Pavan, "Excess Loop Delay Compensation in Continuous-time Delta Sigma Modulators", // IEEE Transactions on Circuits and Systems II : Express Briefs, November 2008.[[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4703533&isnumber=4703515|(paper)]].// | + | * S.Pavan, "Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 55, no. 11, pp. 1119-1123, Nov. 2008. [[https://ieeexplore.ieee.org/document/4703533|doi: 10.1109/TCSII.2008.2008051]] |
| - | * K. Reddy and S.Pavan, "A 20.7 mW Continuous-Time Delta-Sigma Modulator with 15 MHz Bandwidth and 70dB Dynamic Range", //Proceedings of the European Solid State Circuits Conference, Edinburgh//, September 2008.[[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4681829&isnumber=4681770|(paper)]] | + | * K. Reddy and S.Pavan, "A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range," //ESSCIRC 2008 - 34th European Solid-State Circuits Conference//, Edinburgh, 2008, pp. 210-213. [[https://ieeexplore.ieee.org/document/4681829|doi: 10.1109/ESSCIRC.2008.4681829]] |
| - | * S. Pavan, "Power and Area Efficient Adaptive Equalization at Microwave Frequencies", //IEEE Transactions on Circuits and Systems I : Regular Papers,// July 2008.[[http://ieeexplore.ieee.org/iel5/8919/4563499/04447934.pdf?isnumber=4563499&prod=JNL&arnumber=4447934&arSt=1412&ared=1420&arAuthor=Pavan%2C+S.|(paper)]] | + | * S. Pavan, "Power and area-efficient adaptive equalization at microwave frequencies," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 55, no. 6, pp. 1412-1420, July 2008. [[https://ieeexplore.ieee.org/document/4447934|doi: 10.1109/TCSI.2008.918149]] |
| - | * Sudip Shekhar, Jeffrey S. Walling, S. Aniruddhan, and David J. Allstot, "CMOS VCO and LNA using Tuned-Input Tuned-Output circuits", //IEEE Journal of Solid-State Circuits//, vol. 43, no. 5, pp. 1177-1186, May 2008.([[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4494670|paper]]) | + | * Sudip Shekhar, Jeffrey S. Walling, S. Aniruddhan and David J. Allstot, "CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits," //IEEE Journal of Solid-State Circuits//, vol. 43, no. 5, pp. 1177-1186, May 2008. [[https://ieeexplore.ieee.org/document/4494670|doi: 10.1109/JSSC.2008.920360]] |
| - | * S. Pavan, "Power and Area Efficient Analog Adaptive Equalization", //IEEE International Symposium on Circuits and Systems (ISCAS)//, Seattle, May 2008.[[http://ieeexplore.ieee.org/iel5/4534149/4541329/04542120.pdf?tp=&arnumber=4542120&isnumber=4541329|(paper)]] | + | * S. Pavan, "Power and area efficient high speed analog adaptive equalization," //2008 IEEE International Symposium on Circuits and Systems//, Seattle, WA, 2008, pp. 3126-3129. [[https://ieeexplore.ieee.org/document/4542120|doi: 10.1109/ISCAS.2008.4542120]] |
| - | * K. Balemarthy and S. Pavan, "Signal Processing for Optical Fiber Communication", Tutorial at the National Conference on Communication, February 1-3, Bombay, India.{{:publications:ncc08_spavan.pdf|slides}} | + | * K. Balemarthy and S. Pavan, "Signal Processing for Optical Fiber Communication", //Tutorial at the National Conference on Communication//, February 1-3, Bombay, India. [[publications:ncc08_spavan.pdf|slides]] |
| - | * S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, "A Power Optimized Continuous-time Delta-Sigma Modulator for Audio Applications," //IEEE Journal of Solid State Circuits//, February 2008.[[http://ieeexplore.ieee.org/iel5/4/4444554/04444576.pdf?isnumber=4444554&prod=JNL&arnumber=4444576&arSt=351&ared=360&arAuthor=Pavan%2C+S.%3B+Krishnapura%2C+N.%3B+Pandarinathan%2C+R.%3B+Sankar%2C+P.|(paper)]] | + | * S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, "A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications," //IEEE Journal of Solid-State Circuits//, vol. 43, no. 2, pp. 351-360, Feb. 2008. [[https://ieeexplore.ieee.org/document/4444576|doi: 10.1109/JSSC.2007.914263]] |
| - | * S. Pavan and N. Krishnapura, "Oversampling Analog-to-Digital Converters", Full Day Tutorial at the International Conference on VLSI Design, 4-8 January 2008, Hyderabad, India. ([[http://www.ee.iitm.ac.in/~nagendra/videolectures/doku.php?id=200801vlsiconf:start|Lecture and notes]]) | + | * S. Pavan and N. Krishnapura, "Oversampling Analog-to-Digital Converter Design," //21st International Conference on VLSI Design (VLSID 2008)//, Hyderabad, 2008, pp. 7-7. [[https://ieeexplore.ieee.org/document/4450467|doi: 10.1109/VLSI.2008.130]] |
| - | * A. Kokrady, C. P. Ravikumar and N. Chandrachoodan, "Memory Yield Improvement through Multiple Test Sequences and Application aware Fault Models", //21st International Conference on VLSI Design, VLSI 2008, Hyderabad, India//, January 2008. | + | * A. Kokrady, C. P. Ravikumar and N. Chandrachoodan, "Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models," //21st International Conference on VLSI Design (VLSID 2008)//, Hyderabad, 2008, pp. 169-174. [[https://ieeexplore.ieee.org/document/4450498|doi: 10.1109/VLSI.2008.115]] |
| ===== 2007 ===== | ===== 2007 ===== | ||
| - | * P. Sankar and S. Pavan, "Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta-Sigma Modulators", // IEEE Transactions on Circuits and Systems : Express Briefs//, December 2007.[[http://ieeexplore.ieee.org/iel5/8920/4395195/04358635.pdf?tp=&arnumber=4358635&isnumber=4395195|(paper)]] | + | * P. Sankar and S. Pavan, "Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta–Sigma Modulators," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 54, no. 12, pp. 1125-1129, Dec. 2007. [[https://ieeexplore.ieee.org/document/4358635|doi: 10.1109/TCSII.2007.905390]] |
| - | * D.J. Allstot, S. Aniruddhan, M. Chu, N.M. Neihart, D. Ozis, S. Shekhar, and J.S. Walling, "Low Phase Noise CMOS Voltage-controlled Oscillators", (Invited Paper)// Proceedings of 7th International Conference on ASIC (ASICON 2007)//, Guilin, China, October 2007.[[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4415626|(paper)]] | + | * D.J. Allstot, S. Aniruddhan, M. Chu, N.M. Neihart, D. Ozis, S. Shekhar and J.S. Walling, "Low phase noise CMOS voltage-controlled oscillators," //2007 7th International Conference on ASIC//, Guilin, 2007, pp. 297-302. [[https://ieeexplore.ieee.org/document/4415626|doi: 10.1109/ICASIC.2007.4415626]] |
| - | * K. Reddy and S. Pavan, "Fundamental Limitations of Continuous-time Delta Sigma Modulators due to Clock Jitter", // | + | * K. Reddy and S. Pavan, "Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 54, no. 10, pp. 2184-2194, Oct. 2007. [[https://ieeexplore.ieee.org/document/4346678|doi: 10.1109/TCSI.2007.905648]] |
| - | IEEE Transactions on Circuits and Systems : Regular Papers//, October 2007.[[http://ieeexplore.ieee.org/iel5/8919/4346657/04346678.pdf?tp=&arnumber=4346678&isnumber=4346657|(paper)]] | + | * G. Kannan, N. Chandrachoodan and S. Srinivasan, "Rapid Abstract Control Model for Signal Processing Implementation," //2007 IEEE Workshop on Signal Processing Systems//, Shanghai, China, 2007, pp. 418-423. [[https://ieeexplore.ieee.org/document/4387584|doi: 10.1109/SIPS.2007.4387584]] |
| - | * G. Kannan, N. Chandrachoodan and S. Srinivasan, "Rapid Abstract Control Model for Signal Processing Implementation", //IEEE Workshop on Signal Processing Systems, SIPS 2007, Shanghai, China//, October 2007, pp. 418-423. | + | * T. Laxminidhi, V. Prasadu and S. Pavan, "A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS," //2007 IEEE Custom Integrated Circuits Conference//, San Jose, CA, 2007, pp. 683-686. [[https://ieeexplore.ieee.org/document/4405824|doi: 10.1109/CICC.2007.4405824]] |
| - | * T. Laxminidhi, V. Prasadu and S. Pavan, "A Low Power 44-300 MHz Programmable Active-RC Filter in 0.18um CMOS", // Proceedings of the Custom Integrated Circuits Conference//, San Jose, September 2007.[[http://ieeexplore.ieee.org/iel5/4405666/4405667/04405824.pdf?tp=&arnumber=4405824&isnumber=4405667|(paper)]] | + | * S. Pavan, N. Krishnapura, R. Pandarinathan and Prabu Sankar, "A 90μW 15-bit ΔΣ ADC for digital audio," //ESSCIRC 2007 - 33rd European Solid-State Circuits Conference//, Munich, 2007, pp. 198-201. [[https://ieeexplore.ieee.org/document/4430279|doi: 10.1109/ESSCIRC.2007.4430279]] |
| - | * S. Pavan, N. Krishnapura, R. Pandarinathan and Prabu Sankar, "A 90 microwatt 15-bit Continuous-time Sigma Delta ADC for Digital Audio", // Proceedings of the European Solid State | + | * S. Pavan and T. Laxminidhi, "Accurate Characterization of Integrated Continuous-Time Filters," //IEEE Journal of Solid-State Circuits//, vol. 42, no. 8, pp. 1758-1766, Aug. 2007. [[https://ieeexplore.ieee.org/document/4277876|doi: 10.1109/JSSC.2007.900288]] |
| - | Circuits Conference//, Munich, September 2007.[[http://ieeexplore.ieee.org/iel5/4430236/4430237/04430279.pdf?tp=&arnumber=4430279&isnumber=4430237|(paper)]] | + | * K. N. Parashar and N. Chandrachoodan, "A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation," //2007 International Conference on Field Programmable Logic and Applications//, Amsterdam, 2007, pp. 792-795. [[https://ieeexplore.ieee.org/document/4380770|doi: 10.1109/FPL.2007.4380770]] |
| - | * S. Pavan and T. Laxminidhi, "Accurate Characterization of Integrated Continuous Time Filters", // IEEE Journal of Solid State Circuits, August 2007.[[http://ieeexplore.ieee.org/iel5/4/4277855/04277876.pdf?tp=&arnumber=4277876&isnumber=4277855|(paper)]]// | + | * T. Laxminidhi and S. Pavan, "Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 54, no. 7, pp. 1481-1488, July 2007. [[https://ieeexplore.ieee.org/document/4268410|doi: 10.1109/TCSI.2007.899625]] |
| - | * K. N. Parashar and N. Chandrachoodan, "A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation", //17th International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam//, August 2007, pp. 792-795. DOI: 10.1109/FPL.2007.4380770. | + | * S. Shekhar, S. Aniruddhan, and D.J. Allstot, "A Tuned-Input Tuned-Output VCO in 0.18μm CMOS," //2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium//, Honolulu, HI, 2007, pp. 607-610. [[https://ieeexplore.ieee.org/document/4266505|doi: 10.1109/RFIC.2007.380957]] |
| - | * T. Laxminidhi and S. Pavan, "Efficient Design Centering of High Frequency Continuous Time Filters", // IEEE Transactions on Circuits and Systems : Regular Papers, July 2007.[[http://ieeexplore.ieee.org/iel5/8919/4268395/04268410.pdf?tp=&arnumber=4268410&isnumber=4268395|(paper)]] // | + | * T. Laxminidhi and S. Pavan, "Accurate Characterization of Integrated Continuous-Time Filters," //IEEE Journal of Solid-State Circuits//, vol. 42, no. 8, pp. 1758-1766, Aug. 2007. [[https://ieeexplore.ieee.org/document/4277876|doi: 10.1109/JSSC.2007.900288]] |
| - | * S. Shekhar, S. Aniruddhan, and D.J. Allstot, "A Tuned-Input Tuned-Output VCO in 0.18μm CMOS", // 2007 IEEE RFIC Symposium//, Digest of Papers, pp. 607-610, Honolulu, HI, USA, June 2007.[[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4266505|(paper)]] | + | * S. Pavan, "Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive Equalization," //2007 IEEE International Symposium on Circuits and Systems (ISCAS)//, New Orleans, LA, 2007, pp. 3550-3553. [[https://ieeexplore.ieee.org/document/4253447|doi: 10.1109/ISCAS.2007.378449]] |
| - | * T. Laxminidhi and S. Pavan, "Efficiently Design Centering High Frequency Integrated Continuous-time Filters", // | + | * S. Pavan and N. Krishnapura, "Automatic Tuning of Time Constants in Continuous-Time Delta–Sigma Modulators," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 54, no. 4, pp. 308-312, April 2007. [[https://ieeexplore.ieee.org/document/4155068|doi: 10.1109/TCSII.2006.888920]] |
| - | IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans[[http://ieeexplore.ieee.org/iel5/4/4277855/04277876.pdf?tp=&arnumber=4277876&isnumber=4277855|(paper)]]// | + | * S. Pavan and R. Tiruvuru, "Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 54, no. 2, pp. 401-410, Feb. 2007. [[https://ieeexplore.ieee.org/document/4089129|doi: 10.1109/TCSI.2006.887475]] |
| - | * S. Pavan, "Singly Terminated Transmission Line Filters for High Speed Adaptive Equalization", // | + | |
| - | IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans.[[http://ieeexplore.ieee.org/iel5/11145/35661/01692769.pdf?tp=&arnumber=1692769&isnumber=35661|(paper)]]// | + | |
| - | * S. Pavan and N. Krishnapura, "Automatic Tuning of Time-Constants in Continuous-Time Delta-Sigma Modulators", // IEEE Transactions on Circuits and Systems : Express Briefs, April 2007.[[http://ieeexplore.ieee.org/iel5/8920/4155049/04155068.pdf?isnumber=4155049&prod=JNL&arnumber=4155068&arSt=308&ared=312&arAuthor=Shanthi+Pavan%3B+Nagendra+Krishnapura|(paper)]]// | + | |
| - | * S. Pavan and R. Tiruvuru, "Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers" //IEEE Transactions on Circuits and Systems : Regular Papers, February 2007. | + | |
| - | [[http://ieeexplore.ieee.org/iel5/8919/4089106/04089129.pdf?tp=&arnumber=4089129&isnumber=4089106|(paper)]] // | + | |
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| ===== 2006 ===== | ===== 2006 ===== | ||
| - | * K.N.Vikram and V.Vasudevan, "Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures", //IEEE Trans. VLSI design//. September 2006.[[http://ieeexplore.ieee.org/iel5/92/36101/01715333.pdf?tp=&arnumber=1715333&isnumber=36101|(paper)]] | + | * K.N.Vikram and V.Vasudevan, "Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures," //IEEE Transactions on Very Large Scale Integration (VLSI) Systems//, vol. 14, no. 9, pp. 1010-1023, Sept. 2006. [[https://ieeexplore.ieee.org/document/1715333|doi: 10.1109/TVLSI.2006.884052]] |
| - | * V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar, " A Distortion Compensating Flash Analog to Digital Conversion Technique," //IEEE Journal of Solid State Circuits//. September 2006. [[http://ieeexplore.ieee.org/iel5/4/35458/01683888.pdf?tp=&arnumber=1683888&isnumber=35458|(paper)]] | + | * V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar, "A Distortion Compensating Flash Analog-to-Digital Conversion Technique," //IEEE Journal of Solid-State Circuits//, vol. 41, no. 9, pp. 1959-1969, Sept. 2006. [[https://ieeexplore.ieee.org/document/1683888|doi: 10.1109/JSSC.2006.880601]] |
| - | * S. Pavan and T.Laxminidhi, " A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters," Proceedings of the //IEEE Custom Integrated Circuits Conference//, CICC 2006, San Jose, September 2006.[[http://www.ee.iitm.ac.in/~shanthi/cicc06_filter.pdf|(paper)]] | + | * S. Pavan and T.Laxminidhi, "A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters," //IEEE Custom Integrated Circuits Conference 2006//, San Jose, CA, 2006, pp. 77-80. [[https://ieeexplore.ieee.org/document/4114912|doi: 10.1109/CICC.2006.320980]] |
| - | * S. Pavan and T.Laxminidhi, " A 70-500 MHz Programmable CMOS Filter Compensated for MOS Nonquasistatic Effects," Proceedings of the //IEEE European Solid State Circuits Conference//, ESSCIRC 2006, Switzerland, September 2006. [[http://www.ee.iitm.ac.in/~shanthi/esscirc06.pdf|(paper)]] | + | * S. Pavan and T.Laxminidhi, "A 70-500+MHz Programmable CMOS Filter Compensated for MOS Nonquasistatic Effects," //2006 Proceedings of the 32nd European Solid-State Circuits Conference//, Montreux, 2006, pp. 328-331. [[https://ieeexplore.ieee.org/document/4099770|doi: 10.1109/ESSCIR.2006.307597]] |
| - | * S. Murali and S. Pavan," Rapid Simulation of Current Steering DACs using Verilog-A," Proceedings of the //IEEE Custom Integrated Circuits Conference//, CICC 2006, San Jose, September 2006.[[http://www.ee.iitm.ac.in/~shanthi/cicc06_dac.pdf|(paper)]] | + | * S. Murali and S. Pavan, "Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A," //IEEE Custom Integrated Circuits Conference 2006//, San Jose, CA, 2006, pp. 201-204. [[https://ieeexplore.ieee.org/document/4114939|doi: 10.1109/CICC.2006.320910]] |
| - | * Ponnmozhi S. and Nitin Chandrachoodan, "Design of Hardware Coprocessor for OTDR Application", 11th IEEE VLSI Design and Test Symposium, VDAT 2006, Goa, India, August 2006. | + | * Ponnmozhi S. and Nitin Chandrachoodan, "Design of Hardware Coprocessor for OTDR Application", //11th IEEE VLSI Design and Test Symposium//, VDAT 2006, Goa, India, August 2006. |
| - | * S. Shekhar, S. Aniruddhan and D.J. Allstot, "A Fully-Differential CMOS Clapp VCO for IEEE 802.11a Applications", //IEEE International Symposium on Circuits and Systems//, ISCAS 2006, Kos, Greece , May 2006.[[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1693316|(paper)]] | + | * S. Shekhar, S. Aniruddhan and D.J. Allstot, "A fully-differential CMOS Clapp VCO for IEEE 802.11a applications," //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-. [[https://ieeexplore.ieee.org/document/1693316|doi: 10.1109/ISCAS.2006.1693316]] |
| - | * S. Aniruddhan, S. Shekhar and D.J. Allstot, "A Delay Generation Technique for Fast-locking Frequency Synthesizers", //IEEE International Symposium on Circuits and Systems//, ISCAS 2006, Kos, Greece , May 2006.[[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1693870|(paper)]] | + | * S. Aniruddhan, S. Shekhar and D.J. Allstot, "A delay generation technique for fast-locking frequency synthesizers," //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-5466. [[https://ieeexplore.ieee.org/document/1693870|doi: 10.1109/ISCAS.2006.1693870]] |
| - | * A. Sharma and S. Pavan,"A Single Inductor Multiple Output Converter with Adaptive Delta Current Mode Control," //IEEE International Symposium on Circuits and Systems//, ISCAS 2006, Kos, Greece , May 2006.(paper) | + | * A. Sharma and S. Pavan, "A single inductor multiple output converter with adaptive delta current mode control," //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-. [[https://ieeexplore.ieee.org/document/1693915|doi: 10.1109/ISCAS.2006.1693915]] |
| - | * K. Reddy and S. Pavan,"Fundamental Limitations of Continuous-time Delta-Sigma Modulators due to Clock Jitter ," //IEEE International Symposium on Circuits and Systems//, ISCAS 2006, Kos, Greece , May 2006.[[http://ieeexplore.ieee.org/iel5/11145/35661/01693011.pdf?tp=&arnumber=1693011&isnumber=35661|(paper)]] (slides) | + | * K. Reddy and S. Pavan, "Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 54, no. 10, pp. 2184-2194, Oct. 2007. [[https://ieeexplore.ieee.org/document/4346678|doi: 10.1109/TCSI.2007.905648]] |
| - | * T. Rajesh and S. Pavan, "Transmission Line based FIR Structures for High Speed Adaptive Equalization," //IEEE International Symposium on Circuits and Systems//, ISCAS 2006, Kos, Greece , May 2006.[[http://ieeexplore.ieee.org/iel5/11145/35661/01692769.pdf?tp=&arnumber=1692769&isnumber=35661|(paper)]] (slides) | + | * T. Rajesh and S. Pavan, "Transmission line based FIR structures for high speed adaptive equalization," //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-1054. [[https://ieeexplore.ieee.org/document/1692769|doi: 10.1109/ISCAS.2006.1692769]] |
| - | * K.N. Vikram and V. Vasudevan, Scheduling divisible loads on partially reconfigurable hardware, //Proc. IEEE Symposium on Field-Programmable Custom Computing Machines//, Poster Summary, April 2006. | + | * K.N. Vikram and V. Vasudevan, "Scheduling divisible loads on partially reconfigurable hardware," //2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines//, Napa, CA, 2006, pp. 289-290. [[https://ieeexplore.ieee.org/document/4020924|doi: 10.1109/FCCM.2006.63]] |
| - | * P. Rajesh Kumar, K. Sridharan and S. Srinivasan, A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment, Parallel Computing Journal, Elsevier, Vol. 32, No. 3, March 2006, pp. 205-221. | + | * P. Rajesh Kumar, K. Sridharan and S. Srinivasan, "A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment," //Parallel Computing Journal//, Elsevier, Vol. 32, No. 3, March 2006, pp. 205-221. [[https://www.sciencedirect.com/science/article/pii/S0167819105001389|doi: 10.1016/j.parco.2005.09.004]] |
| - | * Kavish Seth, Viswajith, S. Srinivasan and V. Kamakoti, "Ultra Folded High-Speed Architectures for Reed-Solomon Decoders", International Conference on VLSI Design, Hyderabad, Jan 2006. | + | * Kavish Seth, Viswajith, S. Srinivasan and V. Kamakoti, "Ultra folded high-speed architectures for Reed Solomon decoders," //19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)//, Hyderabad, India, 2006, pp. 4 pp.-. [[https://ieeexplore.ieee.org/document/1581506|doi: 10.1109/VLSID.2006.163]] |
| - | * S. Pavan and S. Shivappa," Nonidealities in Traveling Wave and Transversal FIR Filters Operating at Microwave Frequencies ", //IEEE Transactions on Circuits and Systems : Regular Papers// , January 2006. [[http://ieeexplore.ieee.org/iel5/8919/33334/01576897.pdf?tp=&arnumber=1576897&isnumber=33334|(paper)]] | + | * S. Pavan and S. Shivappa, "Nonidealities in traveling wave and transversal FIR filters operating at microwave frequencies," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 53, no. 1, pp. 177-192, Jan. 2006. [[https://ieeexplore.ieee.org/document/1576897|doi: 10.1109/TCSI.2005.854610]] |
| - | * S. Pavan, P. Easwaran and C. Srinivasan,"System Level Aspects of Analog-to-Digital Converter Designs," //International Conference on VLSI Design//, Hyderabad, India, January 2006. (slides) | + | * S. Pavan, P. Easwaran and C. Srinivasan, "System aspects of analog to digital converter designs," //19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)//, Hyderabad, India, 2006, pp. 1 pp.-. [[https://ieeexplore.ieee.org/document/1581413|doi: 10.1109/VLSID.2006.154]] |
| - | * Q. Khan, G. K. Siddhartha, “A Sequence Independent Power-on-Reset Circuit for Multi-Voltage Integrated Systems, 2006 IEEE International Symposium on Circuits and Systems (ISCAS-2006),” Mar, 2006, Greece. | + | * Q. Khan and G. K. Siddhartha, "A sequence independent power-on-reset circuit for multi-voltage systems," //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-. [[https://ieeexplore.ieee.org/document/1692824|doi: 10.1109/ISCAS.2006.1692824]] |
| - | * Q. Khan, G. K. Siddhartha, D. Tripathi, S. K. Wadhwa, K. Misri, “Techniques for on-chip Process, Voltage and Temperature Detection and Compensation,” 19th International Conference on VLSI Design, Jan. 2006, India. | + | * Q. Khan, G. K. Siddhartha, D. Tripathi, S. K. Wadhwa and K. Misri, "Techniques for on-chip process voltage and temperature detection and compensation," //19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)//, Hyderabad, India, 2006, pp. 6 pp.-. [[https://ieeexplore.ieee.org/document/1581519|doi: 10.1109/VLSID.2006.155]] |
| - | * Q. Khan, S. K. Wadhwa, K. Misri, “A single Supply Level Shifter for Multi-Voltage Systems,” 19th International Conference on VLSI Design Jan. 2006, India. | + | * Q. Khan, S. K. Wadhwa and K. Misri, "A single supply level shifter for multi-voltage systems," //19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)//, Hyderabad, India, 2006, pp. 4 pp.-. [[https://ieeexplore.ieee.org/document/1581515|doi: 10.1109/VLSID.2006.24]] |
| - | + | ||
| - | + | ||
| ===== 2005 ===== | ===== 2005 ===== | ||
| - | * K.N.Vikram and V.Vasudevan, "Hardware-software co-simulation of bus-based reconfigurable systems", //Microprocessors and Microsystems//, vol. 29(4), pp 133-144, May 2005. | + | * K.N.Vikram and V.Vasudevan, "Hardware-software co-simulation of bus-based reconfigurable systems", //Microprocessors and Microsystems//, vol. 29(4), pp 133-144, May 2005. [[https://www.sciencedirect.com/science/article/abs/pii/S0141933104000924|doi: 10.1016/j.micpro.2004.07.004]] |
| - | * K.P.Sunil Rafeeque and V.Vasudevan, " A New Technique for on-chip error estimation and reconfiguration of current steering digital to analog converters", //IEEE Trans. Circuits and Systems-I:Regular papers//, Nov. 2005 | + | * K.P.Sunil Rafeeque and V.Vasudevan, " A New Technique for on-chip error estimation and reconfiguration of current steering digital to analog converters," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 52, no. 11, pp. 2348-2357, Nov. 2005. [[https://ieeexplore.ieee.org/document/1528680|doi: 10.1109/TCSI.2005.853587]] |
| - | * N. Krishnapura, M. Barazande-Pour, Q. Chaudhry, J. Khoury, K. Lakshmikumar, A. Aggarwal, "A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission", //IEEE International Solid State Circuits Conference//, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.([[http://www.ee.iitm.ac.in/~nagendra/papers/isscc2005_bpxcvr-pap.pdf|paper]], [[http://www.ee.iitm.ac.in/~nagendra/papers/isscc2005_bpxcvr-sl.pdf|slides]]) | + | * N. Krishnapura, M. Barazande-Pour, Q. Chaudhry, J. Khoury, K. Lakshmikumar and A. Aggarwal, "A 5Gb/s NRZ transceiver with adaptive equalization for backplane transmission," //ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference//, 2005., San Francisco, CA, 2005, pp. 60-585 Vol. 1. [[https://ieeexplore.ieee.org/document/1493868|doi: 10.1109/ISSCC.2005.1493868]] |
| - | * S. Pavan and S. Shivappa," Analysis of Traveling Wave and Transversal Analog Adaptive Equalizers", //IEEE International Symposium on Circuits and Systems//, ISCAS 2005, Kobe , May 2005.[[http://ieeexplore.ieee.org/iel5/9898/31469/01465997.pdf?tp=&arnumber=1465997&isnumber=31469|(paper)]] (slides) | + | * S. Pavan and S. Shivappa, "Analysis of Traveling Wave and Transversal Analog Adaptive Equalizers," //2005 IEEE International Symposium on Circuits and Systems//, Kobe, 2005, pp. 5962-5965 Vol. 6. [[https://ieeexplore.ieee.org/document/1465997|doi: 10.1109/ISCAS.2005.1465997]] |
| - | * S. Pavan, M. Tarsia, S. Kudszus and D. Pritzkau," Design considerations for Integrated Modulator Drivers in SiGe Technology", //International Journal of High Speed Electronics and Systems//, September 2005. | + | * S. Pavan, M. Tarsia, S. Kudszus and D. Pritzkau, "Design considerations for Integrated Modulator Drivers in SiGe Technology," //International Journal of High Speed Electronics and Systems//, Vol. 15, No. 03, pp. 477-495 (2005). [[https://www.worldscientific.com/doi/abs/10.1142/S0129156405003284|doi: 10.1142/S0129156405003284]] |
| - | * D.J. Allstot, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar and K. Soumyanath, "Circuit Techniques for CMOS Multiple-Antenna Transceivers", // 2005 IEEE RFIC Symposium//, Digest of Papers, Long Beach, CA, USA, June 2005.[[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1489639|(paper)]] | + | * D.J. Allstot, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar and K. Soumyanath, "Circuit techniques for CMOS multiple-antenna transceivers," //2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers//, Long Beach, CA, USA, 2005, pp. 225-228. [[https://ieeexplore.ieee.org/document/1489639|doi: 10.1109/RFIC.2005.1489639]] |
| - | * D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh and S. Shekhar,"Recent advances and design trends in CMOS radio frequency integrated Circuits", //International Journal of High Speed Electronics and Systems//, vol.15, no.2, pp 377-428, June 2005. | + | * D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh and S. Shekhar,"Recent advances and design trends in CMOS radio frequency integrated Circuits", //International Journal of High Speed Electronics and Systems//, vol.15, no.2, pp 377-428, June 2005. [[https://www.worldscientific.com/doi/abs/10.1142/9789812774583_0006|doi: 10.1142/9789812774583_0006]] |
| - | * V.Vasudevan, "Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits", //Proc. $42^{nd}$ Design Automation Conference//, pp 397-442, June 2005. | + | * V.Vasudevan, "Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits," //Proceedings. 42nd Design Automation Conference//, 2005., Anaheim, CA, 2005, pp. 397-402. [[https://ieeexplore.ieee.org/document/1510361|doi: 10.1145/1065579.1065685]] |
| - | * S. Aniruddhan and D.J. Allstot, "Architectural Issues in Base-Station Frequency Synthesizers", //IEEE International Symposium on Circuits and Systems//, ISCAS 2005, Kobe , May 2005. [[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1466015|(paper)]] | + | * S. Aniruddhan and D.J. Allstot, "Architectural issues in base-station frequency synthesizers," //2005 IEEE International Symposium on Circuits and Systems//, Kobe, 2005, pp. 6034-6037 Vol. 6. [[https://ieeexplore.ieee.org/document/1466015|doi: 10.1109/ISCAS.2005.1466015]] |
| - | * S. Ramachandran and S. Srinivasan, "Design and FPGA Implementation of an MPEG based Video Scalar with reduced on-chip memory utilization", Journal of Systems Architecture, Elsevier Publications, Vol. 51, pp. 435-450, 2005. | + | * S. Ramachandran and S. Srinivasan, "Design and FPGA Implementation of an MPEG based Video Scalar with reduced on-chip memory utilization", //Journal of Systems Architecture, Elsevier Publications//, Vol. 51, pp. 435-450, 2005. [[https://www.sciencedirect.com/science/article/pii/S1383762104001183|doi: 10.1016/j.sysarc.2004.07.008]] |
| - | * K.N. Vikram, V. Vasudevan and S.Srinivasan, "Rate-distortion estimation for fast JPEG 2000 compression at low bit-rates", Electronics Letters, Vol. 41, No. 1, pp. 16-18, Jan 2005. | + | * K.N. Vikram, V. Vasudevan and S.Srinivasan, "Rate-distortion estimation for fast JPEG2000 compression at low bit-rates," //Electronics Letters//, vol. 41, no. 1, pp. 16-18, 6 Jan. 2005. [[https://ieeexplore.ieee.org/document/1387772|doi: 10.1049/el:20057147]] |
| - | * S.Singh and S.Srinivasan, "Architecturally efficient FFT pruning algorithm", Electronics Letters, Vol. 41, No. 23, pp. 1305-1306, Nov. 2005. | + | * S.Singh and S.Srinivasan, "Architecturally efficient FFT pruning algorithm," //Electronics Letters//, vol. 41, no. 23, pp. 1305-1306, 10 Nov. 2005. [[https://ieeexplore.ieee.org/document/1541788|doi: 10.1049/el:20052994]] |
| - | * P.Rajesh Kumar, K.Sridharan and S.Srinivasan, "An Efficient Algorithm for Topological Map Construction in a Planar Environment Explored using Proximity Sensors", Proceedings of the Second IEEE International Conference on Intelligent Sensing and Information Processing (ICISIP 2005), pp. 67-72, Chennai, India, Jan. 2005. | + | * P.Rajesh Kumar, K.Sridharan and S.Srinivasan, "An efficient algorithm for topological map construction in a planar environment explored using proximity sensors," //Proceedings of 2005 International Conference on Intelligent Sensing and Information Processing//, 2005., Chennai, India, 2005, pp. 67-72. [[https://ieeexplore.ieee.org/document/1529422|doi: 10.1109/ICISIP.2005.1529422]] |
| ===== 2004 ===== | ===== 2004 ===== | ||
| - | * K.P. Sunil Rafeeque and V.Vasudevan, "A Built-In-Self-Test Scheme for Segmented and Binary Weighted DACs", //Journal of Electronic Testing:Theory and Applications//, vol. 20, pp 623-638, Dec. 2004 | + | * K.P. Sunil Rafeeque and V.Vasudevan, "A Built-In-Self-Test Scheme for Segmented and Binary Weighted DACs", //Journal of Electronic Testing:Theory and Applications//, vol. 20, pp 623-638, Dec. 2004. [[https://link.springer.com/article/10.1007%2Fs10677-004-4250-4|doi: 10.1007/s10677-004-4250-4]] |
| - | * K.P.S.Rafeeque and V.Vasudevan, "A Built-in-Self-Test scheme for Digital to Analog Converters", //Proc. 17th International Conference on VLSI design//, pp1027-1032, 2004. | + | * K.P.S.Rafeeque and V.Vasudevan, "A built-in-self-test scheme for digital to analog converters," //17th International Conference on VLSI Design. Proceedings.//, Mumbai, India, 2004, pp. 1027-1032. [[https://ieeexplore.ieee.org/document/1261065|doi: 10.1109/ICVD.2004.1261065]] |
| - | * K.P.Sunil Rafeeque and V.Vasudevan, "An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC", //Proceedings of the 2004 International Symposium on Circuits and Systems//, 2004. ISCAS '04", vol. 1, pp 281-284, May, 2004 | + | * K.P.Sunil Rafeeque and V.Vasudevan, "An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC," //2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)//, Vancouver, BC, 2004, pp. I-I. [[https://ieeexplore.ieee.org/document/1328186|doi: 10.1109/ISCAS.2004.1328186]] |
| - | * N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. "The hierarchical timing pair model for multirate DSP applications.", //IEEE Transactions on Signal Processing//, 52(5):1209-1217, May 2004. | + | * N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, "The hierarchical timing pair model for multirate DSP applications," //IEEE Transactions on Signal Processing//, vol. 52, no. 5, pp. 1209-1217, May 2004. [[https://ieeexplore.ieee.org/document/1284818|doi: 10.1109/TSP.2004.826178]] |
| - | * S. Aniruddhan, M.Chu and D.J. Allstot, "A lateral-BJT-biased CMOS voltage-controlled oscillator", //IEEE International Symposium on Circuits and Systems//, ISCAS 2004, Vancouver, May 2004. [[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1328360|(paper)]] | + | * S. Aniruddhan, M.Chu and D.J. Allstot, "A lateral-BJT-biased CMOS voltage-controlled oscillator," //2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)//, Vancouver, BC, 2004, pp. I-976. [[https://ieeexplore.ieee.org/document/1328360|doi: 10.1109/ISCAS.2004.1328360]] |
| - | * S. Pavan, " A Fixed Transconductance Bias Circuit for CMOS Analog Integrated Circuits", //IEEE International Symposium on Circuits and Systems//, ISCAS 2004, Vancouver , May 2004.(paper) (slides) | + | * S. Pavan, "A fixed transconductance bias technique for CMOS analog integrated circuits," //2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)//, Vancouver, BC, 2004, pp. I-661. [[https://ieeexplore.ieee.org/document/1328281|doi: 10.1109/ISCAS.2004.1328281]] |
| - | * S. Pavan, " Continuous-Time Integrated FIR Filters at Microwave Frequencies", //IEEE Transactions on Circuits and Systems-II, Analog and Digital Signal Processing//, January 2004. (paper) | + | * S. Pavan, "Continuous-time integrated FIR filters at microwave frequencies," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 51, no. 1, pp. 15-20, Jan. 2004. [[https://ieeexplore.ieee.org/document/1263698|doi: 10.1109/TCSII.2003.821522]] |
| - | * V.Vasudevan "A Time-Domain Technique for Computation of Noise Spectral Density in Linear and Non-Linear Time-Varying Circuits", //IEEE Trans. Circuits and Systems-I//, vol 51(2), pp422,433, Feb 2004 | + | * V.Vasudevan, "A time-domain technique for computation of noise-spectral density in linear and nonlinear time-varying circuits," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 51, no. 2, pp. 422-433, Feb. 2004. [[https://ieeexplore.ieee.org/document/1266841|doi: 10.1109/TCSI.2003.822553]] |
| - | * V.Vasudevan "A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory", //IEEE Trans. Circuits and Systems-I:Regular papers//, vol.51(11), pp 2174-2178, Nov. 2004 | + | * V.Vasudevan, "A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 51, no. 11, pp. 2175-2178, Nov. 2004. [[https://ieeexplore.ieee.org/document/1356149|doi: 10.1109/TCSI.2004.836858]] |
| - | * V.Vasudevan and M.Ramakrishna "Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits", //IEEE Trans. Circuits and Systems-I:Regular papers//, vol.51(11), pp 2165-2174, Nov 2004 | + | * V.Vasudevan and M.Ramakrishna "Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 51, no. 11, pp. 2165-2174, Nov. 2004. [[https://ieeexplore.ieee.org/document/1356148|doi: 10.1109/TCSI.2004.836844]] |
| - | * Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, Balakuteswar V. Voleti "A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation" International Conference on VLSI Design, Mumbai, Jan 2004. | + | * Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti and V. Bala Kuteshwar, "A parallel architectural implementation of the New Three-Step Search algorithm for block motion estimation," //17th International Conference on VLSI Design. Proceedings.//, Mumbai, India, 2004, pp. 1071-1076. [[https://ieeexplore.ieee.org/document/1261071|doi: 10.1109/ICVD.2004.1261071]] |
| - | * Q. Khan, S. K. Wadhwa, K. Misri, “A tunable gm-C filter with low variation across process, voltage and temperature, ” 17th International Conference on VLSI Design, Mumbai, India, Jan, 2004, pp. 539-544. | + | * Q. Khan, S. K. Wadhwa and K. Misri, "A tunable g/sub m/-C filter with low variation across process, voltage and temperature," //17th International Conference on VLSI Design. Proceedings.//, Mumbai, India, 2004, pp. 539-544. [[https://ieeexplore.ieee.org/document/1260975|doi: 10.1109/ICVD.2004.1260975]] |
| ===== 2003 ===== | ===== 2003 ===== | ||
| - | * N. Krishnapura and Y. Tsividis, "Micropower low-voltage analog filter in a digital CMOS process", //IEEE Journal of Solid State Circuits//, vol. 38, no. 6, pp. 1063-1067, Jun. 2003. (paper) | + | * N. Krishnapura and Y. Tsividis, "Micropower low-voltage analog filter in a digital CMOS process," //IEEE Journal of Solid-State Circuits//, vol. 38, no. 6, pp. 1063-1067, June 2003. [[https://ieeexplore.ieee.org/document/1202011|doi: 10.1109/JSSC.2003.811986]] |
| - | * S. Kudszus, A. Shahani, S.Pavan, D. Schaffer and M. Tarsia, " A 46-GHz Distributed Transimpedance Amplifier using SiGe Bipolar Technology ", //Proceedings of the International Microwave Symposium//, Philadelphia, May 2003.(paper) | + | * S. Kudszus, A. Shahani, S.Pavan, D. Schaffer and M. Tarsia, "A 46-GHz distributed transimpedance amplifier using SiGe bipolar technology," //IEEE MTT-S International Microwave Symposium Digest//, 2003, Philadelphia, PA, USA, 2003, pp. 1387-1390 vol.2. [[https://ieeexplore.ieee.org/document/1212630|doi: 10.1109/MWSYM.2003.1212630]] |
| - | * S. Pavan, " Analog FIR Filters at Microwave Frequencies ", //Proceedings of the National Conference on Communications//, IIT Madras, Chennai, February 2003.(paper) | + | * S. Pavan, " Analog FIR Filters at Microwave Frequencies," //Proceedings of the National Conference on Communications//, IIT Madras, Chennai, February 2003. [[https://ieeexplore.ieee.org/document/1263698|paper]] |
| - | * V.Vasudevan and M.Ramakrishna, "Computation of Noise Spectral Density in Switched Capacitor Circuits using the Mixed-Frequency-Time Technique", //Proc. $40^{th}$ Design Automation Conference//, June 2003 | + | * V.Vasudevan and M.Ramakrishna, "Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique," //Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)//, Anaheim, CA, 2003, pp. 538-541. [[https://ieeexplore.ieee.org/document/1219065|doi: 10.1145/775832.775968]] |
| - | * V.Vasudevan, "A Time-Domain Technique for Computation of Noise Spectral Density in Switched Capacitor Circuits", //Proc.of the 2003 International Symposium on Circuits and Systems//, ISCAS 2003, Vol 1., pp 585-588. | + | * V.Vasudevan, "A time-domain technique for computation of noise spectral density in switched capacitor circuits," //Proceedings of the 2003 International Symposium on Circuits and Systems//, 2003. ISCAS '03., Bangkok, 2003, pp. I-I.. [[https://ieeexplore.ieee.org/document/1205631|doi: 10.1109/ISCAS.2003.1205631]] |
| - | * Y. Tsividis, N. Krishnapura, Y. Palaskas, L. Toth, "Internally varying analog circuits minimize power dissipation" //IEEE Circuits and Devices Magazine//, vol. 19, no. 1, pp. 63-72, Jan. 2003. (paper) | + | * Y. Tsividis, N. Krishnapura, Y. Palaskas and L. Toth, "Internally varying analog circuits minimize power dissipation," //IEEE Circuits and Devices Magazine//, vol. 19, no. 1, pp. 63-72, Jan. 2003. [[https://ieeexplore.ieee.org/document/1175109|doi: 10.1109/MCD.2003.1175109]] |
| - | * Srikar Movva and S. Srinivasan, "A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI implementation", Sixteenth International Conference on VLSI Design, New Delhi, India, Jan., 2003. | + | * Srikar Movva and S. Srinivasan, "A novel architecture for lifting-based discrete wavelet transform for JPEG2000 standard suitable for VLSI implementation," //16th International Conference on VLSI Design//, 2003. Proceedings., New Delhi, India, 2003, pp. 202-207. [[https://ieeexplore.ieee.org/document/1183137|doi: 10.1109/ICVD.2003.1183137]] |
| - | * K. Gupta and S. Srinivasan, " Reduced Memory Implementation of Modified Serial Watershed Algorithm Based on Queue", International Conference on information Technology: Coding and Computing, Las Vegas, April 2003. | + | * K. Gupta and S. Srinivasan, "Reduced memory implementation of modified serial watershed algorithm based on ordered queue," //Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing//, Las Vegas, NV, USA, 2003, pp. 514-518. [[https://ieeexplore.ieee.org/document/1197582|doi: 10.1109/ITCC.2003.1197582]] |
| - | * A. Kishore and S. Srinivasan, " A Distributed Memory Architecture for Morphological Image Processing", International Conference on information Technology: Coding and Computing, Las Vegas, April 2003 | + | * A. Kishore and S. Srinivasan, "A distributed memory architecture for morphological image processing," //Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing//, Las Vegas, NV, USA, 2003, pp. 536-540. [[https://ieeexplore.ieee.org/document/1197586|doi: 10.1109/ITCC.2003.1197586]] |
| - | * S. Ramachandran and S. Srinivasan, "Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization", Euromicro symposium on Digital System Design, Belek, Turkey, pp. 206-213, September 2003. | + | * S. Ramachandran and S. Srinivasan, "Design and FPGA implementation of a video scalar with on-chip reduced memory utilization," //Euromicro Symposium on Digital System Design//, 2003. Proceedings., Belek-Antalya, Turkey, 2003, pp. 206-213. [[https://ieeexplore.ieee.org/document/1231927|doi: 10.1109/DSD.2003.1231927]] |
| - | * P.Rajesh Kumar, N. Sudha, S. Srinivasan and K. Sridharan " A Pipelined Cellular Architecture For Euclidean Distance Transform", TENCON-2003, Bangalore , 2003 | + | * P.Rajesh Kumar, N. Sudha, S. Srinivasan and K. Sridharan, "A pipelined cellular architecture for Euclidean distance transform," //TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region//, Bangalore, India, 2003, pp. 1153-1156 Vol.3. [[https://ieeexplore.ieee.org/document/1273428|doi: 10.1109/TENCON.2003.1273428]] |
| - | * Q. Khan, D. Dutta, “A Programmable CMOS Bandgap Voltage Reference Circuit using Current Conveyor,” 10th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2003, UAE, Dec. 2003, pp. 8-11, vol.1. | + | * Q. Khan and D. Dutta, "A programmable CMOS bandgap voltage reference circuit using current conveyor," //10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003//, Sharjah, 2003, pp. 8-11 Vol.1. [[https://ieeexplore.ieee.org/document/1301963|doi: 10.1109/ICECS.2003.1301963]] |
| - | * Q. Khan, S. Wadhwa, K. Misri, “Low Power Startup Circuits for Voltage and Current Reference with zero steady state current,” International Symposium on Low Power Electronics and Design (ISLPED), Seoul, Korea, August 2003, pp. 184-188. | + | * Q. Khan, S. Wadhwa and K. Misri, “Low power startup circuits for voltage and current reference with zero steady state current," //Proceedings of the 2003 International Symposium on Low Power Electronics and Design//, 2003. ISLPED '03., Seoul, South Korea, 2003, pp. 184-188. [[https://ieeexplore.ieee.org/document/1231859|doi: 10.1109/LPE.2003.1231859]] |
| - | * Q. Khan, S. Wadhwa, K. Misri, “A Low Voltage Switched-Capacitor Current Reference Circuit with low dependence on Process, Voltage and Temperature,” 16th International Conference on VLSI Design, New Delhi, India, Jan, 2003, pp. 504-506. | + | * Q. Khan, S. Wadhwa and K. Misri, "A low voltage switched-capacitor current reference circuit with low dependence on process, voltage and temperature," //16th International Conference on VLSI Design, 2003. Proceedings.//, New Delhi, India, 2003, pp. 504-506. [[https://ieeexplore.ieee.org/document/1183184|doi: 10.1109/ICVD.2003.1183184]] |
| ===== 2002 ===== | ===== 2002 ===== | ||
| - | * N. Chandrachoodan, "Performance Analysis and Hierarchical Timing for DSP System Synthesis", PhD thesis, Department of Electrical and Computer Engineering, University of Maryland, College Park, August 2002. | + | * N. Chandrachoodan, "Performance Analysis and Hierarchical Timing for DSP System Synthesis", //PhD thesis, Department of Electrical and Computer Engineering//, University of Maryland, College Park, August 2002. [[https://www.semanticscholar.org/paper/Performance-analysis-and-hierarchical-timing-for-Chandrachoodan-Bhattacharyya/8db39615c787ed4fd9cd318b777b6e7203bca182|Paper]] |
| - | * N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. "High-level synthesis of DSP applications using adaptive negative cycle detection.", //EURASIP Journal on Applied Signal Processing//, 2002(9):893-907, September 2002. | + | * N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. "High-level synthesis of DSP applications using adaptive negative cycle detection.", //EURASIP Journal on Applied Signal Processing//, 2002(9):893-907, September 2002. [[https://asp-eurasipjournals.springeropen.com/articles/10.1155/S1110865702205053|doi: 10.1155/S1110865702205053]] |
| - | * S.Ramachandran and S.Srinivasan, "A fast FPGA-based MPEG-2 image encoder with a novel automatic quality control scheme" Elsevier Science, Microprocessors and Microsystems, Vol.25, pp. 449-457, 2002 | + | * S.Ramachandran and S.Srinivasan, "A fast FPGA-based MPEG-2 image encoder with a novel automatic quality control scheme" //Elsevier Science, Microprocessors and Microsystems//, Vol.25, pp. 449-457, 2002 [[https://www.sciencedirect.com/science/article/abs/pii/S0141933101001387|doi: 10.1016/S0141-9331(01)00138-7]] |
| - | * S. Ramachandran and S. Srinivasan, "A novel automatic quality control scheme for real time image transmission." VLSI Design Journal, USA, Vol. 14(4), pp. 329-335, 2002 | + | * S. Ramachandran and S. Srinivasan, "A novel automatic quality control scheme for real time image transmission," //VLSI Design Journal//, USA, Vol. 14(4), pp. 329-335, 2002. [[https://www.hindawi.com/journals/vlsi/2002/969250|doi: 10.1080/10655140290011131]] |
| - | * S. Ramachandran and S. Srinivasan, A dynamically reconfigurable video compression scheme using FPGAs with coarse-grain parallelism", VLSI Design Journal, USA Vol. 15(2), pp. 521-528, 2002. | + | * S. Ramachandran and S. Srinivasan, "A dynamically reconfigurable video compression scheme using FPGAs with coarse-grain parallelism", //VLSI Design Journal//, USA Vol. 15(2), pp. 521-528, 2002. [[https://www.hindawi.com/journals/vlsi/2002/279047/|doi: 10.1080/1065514021000012138]] |
| - | * K. Seth and S. Srinivasan, "Data scheduling scheme for power reduction in DWT-based image coders", Electronics Letters, Vol. 38, No.9, pp 408-409, April 2002. | + | * K. Seth and S. Srinivasan, "Data scheduling scheme for power reduction in DWT-based image coders," //Electronics Letters//, vol. 38, no. 9, pp. 408-409, 25 April 2002. [[https://ieeexplore.ieee.org/document/1001541|doi: 10.1049/el:20020291]] |
| - | * Kavish Seth and S.Srinivasan, "VLSI Implementation of 2-D DWT/IDWT Cores using 9/7 - tap filter banks based on the Non-expansive Symmetric Extension Scheme", Fifteenth International Conference on VLSI Design, 2002. | + | * Kavish Seth and S.Srinivasan, "VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme," //Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design//, Bangalore, India, 2002, pp. 435-440. [[https://ieeexplore.ieee.org/abstract/document/994959|doi: 10.1109/ASPDAC.2002.994959]] |
| ===== 2001 ===== | ===== 2001 ===== | ||
| - | * D. Frey, Y. Tsividis, G. Efthivoulidis, and N. Krishnapura, "Syllabic-companding Log Domain Filters", //IEEE Transactions on Circuits and Systems II//, vol 48, no. 4, pp. 329-339, Apr. 2001.(paper) | + | * D. Frey, Y. Tsividis, G. Efthivoulidis and N. Krishnapura, "Syllabic-companding log domain filters," //IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing//, vol. 48, no. 4, pp. 329-339, April 2001. [[https://ieeexplore.ieee.org/document/933791|doi: 10.1109/82.933791]] |
| - | * G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. Martin, P. Wu and S. Pavan, " A 165 Msps 8 bit CMOS A/D Converter with Background Offset Cancellation ", //Proceedings of the Custom Integrated Circuits Conference//, May 2001. (paper) | + | * G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. Martin, P. Wu and S. Pavan, "A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation," //Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)//, San Diego, CA, 2001, pp. 153-156. [[https://ieeexplore.ieee.org/document/929745|doi: 10.1109/CICC.2001.929745]] |
| - | * N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. "Adaptive negative cycle detection in dynamic graphs.", In //Proceedings of the International Symposium on Circuits and Systems//, pages V-163-V-166, Sydney, Australia, May 2001. | + | * N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, "Adaptive negative cycle detection in dynamic graphs," //ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)//, Sydney, NSW, 2001, pp. 163-166 vol. 5. [[https://ieeexplore.ieee.org/document/922010|doi: 10.1109/ISCAS.2001.922010]] |
| - | * N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. "An efficient timing model for hardware implementation of multirate dataflow graphs.", In //Proceedings of the International Conference on Acoustics, Speech, and Signal Processing//, Salt Lake City, Utah, May 2001. | + | * N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, "An efficient timing model for hardware implementation of multirate dataflow graphs," //2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221)//, Salt Lake City, UT, USA, 2001, pp. 1153-1156 vol.2. [[https://ieeexplore.ieee.org/document/941126|doi: 10.1109/ICASSP.2001.941126]] |
| - | * N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. "The hierarchical timing pair model.", In //Proceedings of the International Symposium on Circuits and Systems//, pages V-367-V-370, Sydney, Australia, May 2001. | + | * N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, "The hierarchical timing pair model.", //Proceedings of the International Symposium on Circuits and Systems//, pages V-367-V-370, Sydney, Australia, May 2001. [[https://www.researchgate.net/publication/221377182_The_hierarchical_timing_pair_model|doi:10.1109/ISCAS.2001.922061]] |
| - | * N. Krishnapura and Y. Tsividis, "A Micropower Log-Domain Filter Using Enhanced Lateral PNPs in a 0.25um CMOS Process", //2001 VLSI Symposium on Circuits//, pp. 179-182, Jun. 16 2001, Kyoto, Japan.(paper, slides) | + | * N. Krishnapura and Y. Tsividis, "A micropower log-domain filter using enhanced lateral PNPs in a 0.25 /spl mu/m CMOS process," //2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)//, Kyoto, Japan, 2001, pp. 179-182. [[https://ieeexplore.ieee.org/document/934231|doi: 10.1109/VLSIC.2001.934231]] |
| - | * N. Krishnapura and Y. Tsividis, "Dynamically Biased 1MHz Low-pass Filter with 61dB peak SNR and 112dB Input Range", //IEEE International Solid State Circuits Conference//, pp. 360-361,465, slide supplement pp. 292-293,507, Feb. 4-7 2001, San Fransisco, USA.(paper, slides) | + | * N. Krishnapura and Y. Tsividis, "Dynamically biased 1 MHz low-pass filter with 61 dB peak SNR and 112 dB input range," //2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)//, San Francisco, CA, USA, 2001, pp. 360-361. [[https://ieeexplore.ieee.org/document/912673|doi: 10.1109/ISSCC.2001.912673]] |
| - | * N. Krishnapura and Y. Tsividis, "Noise and Power Reduction in Filters Through the Use of Adjustable Biasing", //IEEE Journal of Solid State Circuits//, vol. 36, no. 12, pp. 1912-1920, Dec. 2001. (paper) | + | * N. Krishnapura and Y. Tsividis, "Noise and power reduction in filters through the use of adjustable biasing," //IEEE Journal of Solid-State Circuits//, vol. 36, no. 12, pp. 1912-1920, Dec. 2001. [[https://ieeexplore.ieee.org/document/972141|doi: 10.1109/4.972141]] |
| - | * S.Ramachandran and S.Srinivasan, "FPGA Implementation of a Novel, Fast Motion Estimation Algorithm for Real-Time Video Compression.", Ninth International Symposium on Field Programmable Gate Arrays , Monterey, California, USA, Feb., 2001 | + | * S.Ramachandran and S.Srinivasan, "FPGA Implementation of a Novel, Fast Motion Estimation Algorithm for Real-Time Video Compression," //Ninth International Symposium on Field Programmable Gate Arrays//, Monterey, California, USA, Feb., 2001. [[https://dl.acm.org/doi/10.1145/360276.360358|doi: 10.1145/360276.360358]] |
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| ===== 2000 ===== | ===== 2000 ===== | ||
| - | * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, "A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process", // IEEE Journal of Solid State Circuits,// December 2000. | + | * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, "A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process", //IEEE Journal of Solid State Circuits//, December 2000. [[https://link.springer.com/chapter/10.1007%2F978-1-4757-3198-9_2|doi:10.1007/978-1-4757-3198-9_2]] |
| - | * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, " A 700 Msps 6 bit Read Channel A/D Converter with 7 bit Servo Mode", International Solid State Circuits Conference, February 2000. (paper) | + | * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, "A 700M Sample/s 6 b read channel A/D converter with 7 b servo mode," //2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)//, San Francisco, CA, USA, 2000, pp. 426-427. [[https://ieeexplore.ieee.org/document/839844|doi: 10.1109/ISSCC.2000.839844]] |
| - | * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, " A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS", Ninth Workshop on Advances in Analog Circuit Design, Tegernsee, Germany , April 2000. | + | * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, "A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS", //Ninth Workshop on Advances in Analog Circuit Design//, Tegernsee, Germany , April 2000. [[https://link.springer.com/chapter/10.1007%2F978-1-4757-3198-9_2|doi:10.1007/978-1-4757-3198-9_2]] |
| - | * N. Krishnapura and P. Kinget, "A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS", IEEE Journal of Solid State Circuits, vol. 35, no. 7, pp. 1019-1024, Jul. 2000. (paper) | + | * N. Krishnapura and P. Kinget, "A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS," //IEEE Journal of Solid-State Circuits//, vol. 35, no. 7, pp. 1019-1024, July 2000. [[https://ieeexplore.ieee.org/document/848211|doi: 10.1109/4.848211]] |
| - | * N. Krishnapura, Y. Tsividis, and D. R. Frey, "Simplified Technique for Syllabic Companding in Log-domain Filters", Electronics Letters, vol. 36, no. 15, pp. 1257-1259, 20th Jul. 2000.(paper) | + | * N. Krishnapura, Y. Tsividis and D. R. Frey, "Simplified technique for syllabic companding in log-domain filters," //Electronics Letters//, vol. 36, no. 15, pp. 1257-1259, 20 July 2000. [[https://ieeexplore.ieee.org/document/856190|doi: 10.1049/el:20000978]] |
| - | * S. Pavan and Y. Tsividis, "Time Scaled Electrical Networks - Properties and Applications in the Design of Programmable Analog Filters", IEEE Transactions on Circuits and Systems - Analog and Digital Signal Processing, , Vol. 47, No.2, pp. 161-5, February 2000.(paper) | + | * S. Pavan and Y. Tsividis, "Time-scaled electrical networks. Properties and applications in the design of programmable analog filters," //IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing//, vol. 47, no. 2, pp. 161-165, Feb. 2000. [[https://ieeexplore.ieee.org/document/823547|doi: 10.1109/82.823547]] |
| - | * S. Pavan, Y. Tsividis and K. Nagaraj, " Widely Programmable High Frequency Continuous Time Filters in Digital CMOS Technology", IEEE Journal of Solid State Circuits,, Vol. 35, No.4, April 2000.(paper) | + | * S. Pavan, Y. Tsividis and K. Nagaraj, "Widely programmable high-frequency continuous-time filters in digital CMOS technology," //IEEE Journal of Solid-State Circuits//, vol. 35, no. 4, pp. 503-511, April 2000. [[https://ieeexplore.ieee.org/document/839910|doi: 10.1109/4.839910]] |
| - | * Shrenik Patel and S.Srinivasan, "A modified EZW algorithm for fast implementation of a wavelet-based image codec", accepted for publication in Electronics Letters, Vol. 36, No.20, pp. 1713-1714, 2000 | + | * Shrenik Patel and S.Srinivasan, ""Modified embedded zerotree wavelet algorithm for fast implementation of wavelet image codec," //Electronics Letters//, vol. 36, no. 20, pp. 1713-1714, 28 Sept. 2000. [[https://ieeexplore.ieee.org/document/882020|doi: 10.1049/el:20001212]] |
| - | * S.Ramachandran and S.Srinivasan, "A Programmable Pruning Level Control based MPEG Video Encoder", International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland, May 2000. | + | * S.Ramachandran and S.Srinivasan, "A programmable pruning level control based MPEG video encoder," //2000 IEEE International Symposium on Circuits and Systems (ISCAS)//, Geneva, Switzerland, 2000, pp. 571-574 vol.1. [[https://ieeexplore.ieee.org/document/857159|doi: 10.1109/ISCAS.2000.857159]] |
| - | * S.Ramachandran and S.Srinivasan, "Design and Implementation of an EPLD - based Variable Length Coder for Real Time Image Compression Applications", International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland, May, 2000. | + | * S.Ramachandran and S.Srinivasan, "Design and implementation of an EPLD-based variable length coder for real time image compression applications," //2000 IEEE International Symposium on Circuits and Systems (ISCAS)//, Geneva, Switzerland, 2000, pp. 607-610 vol.1. [[https://ieeexplore.ieee.org/document/857168|doi: 10.1109/ISCAS.2000.857168]] |
| ===== 1999 ===== | ===== 1999 ===== | ||
| - | * N. Krishnapura and P. Kinget, "A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS", European Solid State Circuits Conference, pp. 144-147, Sep 21-23 1999, Duisburg, Germany. (paper, slides) | + | * N. Krishnapura and P. Kinget, "A 5.3GHz programmable divider for HiPerLAN in 0.25 µm CMOS," //Proceedings of the 25th European Solid-State Circuits Conference//, Duisburg, Germany, 1999, pp. 142-145. [[https://ieeexplore.ieee.org/document/1471116|Paper]] |
| - | * S. Pavan, Y. Tsividis and K. Nagaraj, " A 60-350 MHz Programmable Analog Filter in a Digital CMOS Process", Proceedings of the European Solid State Circuits Conference,, September 21-23 1999, Duisburg, Germany.(paper, slides) | + | * S. Pavan, Y. Tsividis and K. Nagaraj, "A 60-350 MHz programmable analog filter in a digital CMOS process," //Proceedings of the 25th European Solid-State Circuits Conference//, Duisburg, Germany, 1999, pp. 46-49. [[https://ieeexplore.ieee.org/document/1471092|Paper]] |
| - | * S. Pavan, Y. Tsividis and K. Nagaraj, "Modeling of Accumulation MOS Capacitors for Analog Design in Digital VLSI Processes", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 143-146, May 31-June 3 1999, Orlando, Florida.(paper, slides ) | + | * S. Pavan, Y. Tsividis and K. Nagaraj, "Modeling of accumulation MOS capacitors for analog design in digital VLSI processes," //1999 IEEE International Symposium on Circuits and Systems (ISCAS)//, Orlando, FL, 1999, pp. 202-205 vol.6. [[https://ieeexplore.ieee.org/document/780130|doi: 10.1109/ISCAS.1999.780130]] |
| - | * D.V.R. Murthy, S. Ramachandran and S. Srinivasan, " Parallel Implementation Of 2D-Discrete Cosine Transform Using ELPDs", Twelfth International Conference on VLSI Design, Goa, Jan 1999. | + | * D.V.R. Murthy, S. Ramachandran and S. Srinivasan, "Parallel implementation of 2D-discrete cosine transform using EPLDs," //Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)//, Goa, India, 1999, pp. 336-339. [[https://ieeexplore.ieee.org/document/745178|doi: 10.1109/ICVD.1999.745178]] |
| - | * S.Ramachandran, S.Srinivasan and R.Chen, "EPLD-based Architecture of Real Time 2D-Discrete Cosine Transform and quantization for Image Compression", International Symposium on Circuits and Systems (ISCAS '99), Orlando, Florida, May - June 1999. | + | * S.Ramachandran, S.Srinivasan and R.Chen, "EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression," //1999 IEEE International Symposium on Circuits and Systems (ISCAS)//, Orlando, FL, 1999, pp. 375-378 vol.3. [[https://ieeexplore.ieee.org/document/778863|doi: 10.1109/ISCAS.1999.778863]] |
| - | * T.G.Venkatesh and S.Srinivasan, "A Pruning based fast rate control algorithm for MPEG coding", Third International Conference on Computational Intelligence and Multimedia Applications (ICCIMA'99), New Delhi, Aug. 1999. | + | * T.G.Venkatesh and S.Srinivasan, "A pruning based fast rate control algorithm for MPEG coding," //Proceedings Third International Conference on Computational Intelligence and Multimedia Applications. ICCIMA'99 (Cat. No.PR00300)//, New Delhi, India, 1999, pp. 403-407. [[https://ieeexplore.ieee.org/document/798564|doi: 10.1109/ICCIMA.1999.798564]] |
| ===== 1998 ===== | ===== 1998 ===== | ||
| - | * L. Toth, Y. Tsividis, and N. Krishnapura, "Analysis of Noise and Interference in Companding Signal Processors", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 143-146, Jun 1-3 1998, Monterey, California. (paper, slides) | + | * L. Toth, Y. Tsividis and N. Krishnapura, "Analysis of noise and interference in companding signal processors," //1998 IEEE International Symposium on Circuits and Systems (ISCAS)//, Monterey, CA, 1998, pp. 143-146 vol.1. [[https://ieeexplore.ieee.org/document/704209|doi: 10.1109/ISCAS.1998.704209]] |
| - | * L. Toth, Y. Tsividis, and N. Krishnapura, "On the Analysis of Noise and Interference in Instantaneously Companding Signal Processors", IEEE Transactions on Circuits and systems-II, vol. 45, no. 9, pp. 1242-1249, Sep. 1998. (paper) | + | * L. Toth, Y. Tsividis and N. Krishnapura, "On the analysis of noise and interference in instantaneously companding signal processors," //IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing//, vol. 45, no. 9, pp. 1242-1249, Sept. 1998. [[https://ieeexplore.ieee.org/document/718591|doi: 10.1109/82.718591]] |
| - | * N. Krishnapura, S. Pavan, C. Mathiazhagan, and B. Ramamurthi, "A Baseband Pulse Shaping Method for Gaussian Minimum Shift Keying", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 249-252, Jun 1-3 1998, Monterey, California. (paper, slides) | + | * N. Krishnapura, S. Pavan, C. Mathiazhagan and B. Ramamurthi, "A baseband pulse shaping filter for Gaussian minimum shift keying," //1998 IEEE International Symposium on Circuits and Systems (ISCAS)//, Monterey, CA, 1998, pp. 249-252 vol.1. [[https://ieeexplore.ieee.org/document/704333|doi: 10.1109/ISCAS.1998.704333]] |
| - | * N. Krishnapura, Y. Tsividis, K. Nagaraj, and K. Suyama, "Switched Capacitor Companding Filters", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 480-483, Jun 1-3 1998, Monterey, California. (paper, slides) | + | * N. Krishnapura, Y. Tsividis, K. Nagaraj and K. Suyama, "Companding switched capacitor filters," //ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)//, Monterey, CA, 1998, pp. 480-483 vol.1. [[https://ieeexplore.ieee.org/document/704507|doi: 10.1109/ISCAS.1998.704507]] |
| - | * S. Pavan and Y. Tsividis, "An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 480-483, Jun 1-3 1998, Monterey, California.(paper) | + | * S. Pavan and Y. Tsividis, "An analytical solution for a class of oscillators, and its application to filter tuning," //IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications//, vol. 45, no. 5, pp. 547-556, May 1998. [[https://ieeexplore.ieee.org/document/668866|doi: 10.1109/81.668866]] |
| - | * S. Pavan and Y. Tsividis, "An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning", IEEE Transactions on Circuits and Systems-I, vol. 45, no. 9, pp. 1242-1249, May 1998. (paper) | + | * S. Pavan and Y. Tsividis, "An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning", //IEEE Transactions on Circuits and Systems-I//, vol. 45, no. 9, pp. 1242-1249, May 1998. [[https://ieeexplore.ieee.org/document/668866|doi: 10.1109/81.668866]] |
| - | * S. Venkatesh and S. Srinvasan, "A Modified Butterfly Structure For Efficient Implementation Of Pruned Cosine Transform", Electronics Letters, Vol. 34, No.14, pp. 1383-1385, July 1998 | + | * S. Venkatesh and S. Srinvasan, "Modified butterfly structure for efficient implementation of pruned fast cosine transform," //Electronics Letters//, vol. 34, no. 14, pp. 1383-1385, 9 July 1998. [[https://ieeexplore.ieee.org/document/706082|doi: 10.1049/el:19980977]] |
| - | * S. Srinivasan and B. Srikanth, "Implementation Of A Fast Data Access Architecture For Two Dimensional Applications, International Conference on Computational Intelligence and Multimedia Applications, Churchill, Australia, Feb 1998. | + | * S. Srinivasan and B. Srikanth, "Implementation Of A Fast Data Access Architecture For Two Dimensional Applications, //International Conference on Computational Intelligence and Multimedia Applications//, Churchill, Australia, Feb 1998. |
| - | * S. Venkatesh, S. Srinivasan and R.Chen. "An Efficient Implementation Of A Progressive Image Transmission System Using Successive Pruning Algorithm On A Parallel Architecture", Intl. Conf. On High Performance Computing, Madras, India, Dec 1998. | + | * S. Venkatesh, S. Srinivasan and R.Chen, "An efficient implementation of a progressive image transmission system using successive pruning algorithm on a parallel architecture," //Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238)//, Madras, India, 1998, pp. 445-451. [[https://ieeexplore.ieee.org/document/738020|doi: 10.1109/HIPC.1998.738020]] |
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| ====== Patents ====== | ====== Patents ====== | ||
| - | * M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker, T. Sutton, Current measurments in switching regulators, US 9,755,518, September 5, 2017. | + | * M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker and T. Sutton, "Current measurments in switching regulators", US 9,755,518, September 5, 2017. [[https://patents.google.com/patent/US9755518|US9755518B2]] |
| - | * M. Bansal, Q. Khan, C. Shi, Average current mode control of multi-phase switching power converters, US 9,442,140, Sep. 13, 2016. | + | * M. Bansal, Q. Khan and C. Shi, "Average current mode control of multi-phase switching power converters," US 9,442,140, Sep. 13, 2016. [[https://patents.google.com/patent/JP6185194B2/en|JP6185194B2]] |
| - | * Q. Khan, S. Dhar, J. Zazzera, T. Sutton, Circuits and Methods for Driving Resonant Actuators, US 9,344,022, May 17, 2016. | + | * Qadeer A. Khan,Sandeep Chaman Dhar,Joshua A. ZAZZERA,Todd R. Sutton, "Circuits and Methods for Driving Resonant Actuators," US 9,344,022, May 17, 2016. [[https://patents.google.com/patent/WO2015038703A1|WO2015038703A1]] |
| - | * Davinder Aggarwal, Vibhor Jain, Janakiraman VIRARAGHAVAN, "Automated design rule checking (DRC) test case generation", US 8,875,064, Oct 28, 2014. | + | * Davinder Aggarwal, Vibhor Jain and Janakiraman VIRARAGHAVAN, "Automated design rule checking (DRC) test case generation," US 8,875,064, Oct 28, 2014. [[https://patents.google.com/patent/US8875064B2/en|US8875064B2]] |
| - | * Davinder Aggarwal, Vaibhav A. RUPARELIA, Neha Singh, Janakiraman VIRARAGHAVAN, "Generic design rule checking (DRC) test case extraction", US 9,292,652, Mar 22 2016. | + | * Davinder Aggarwal, Vaibhav A. RUPARELIA, Neha Singh and Janakiraman VIRARAGHAVAN, "Generic design rule checking (DRC) test case extraction", US 9,292,652, Mar 22 2016. [[https://patents.google.com/patent/US9292652|US9292652B2]] |
| - | * C. Narathong and S. Aniruddhan, "Multi-mode Configurable Transmitter Circuit", US 8,099,127, Jan. 17, 2012. | + | * C. Narathong and S. Aniruddhan, "Multi-mode Configurable Transmitter Circuit", US 8,099,127, Jan. 17, 2012. [[https://patents.google.com/patent/US8099127|US8099127B2]] |
| - | * C. Narathong, S. Aniruddhan and W. Su, "Amplifier with Gain Expansion Stage", US 8,035,443, Oct. 11, 2011. | + | * C. Narathong, S. Aniruddhan and W. Su, "Amplifier with Gain Expansion Stage", US 8,035,443, Oct. 11, 2011. [[https://patents.google.com/patent/US8035443B2/en|US8035443B2]] |
| - | * B. Sun, S. Aniruddhan and S. Sridhara, "Method and Apparatus for Divider Unit Synchronization", US 7,965,111, Jun. 25, 2011. | + | * B. Sun, S. Aniruddhan and S. Sridhara, "Method and Apparatus for Divider Unit Synchronization", US 7,965,111, Jun. 25, 2011. [[https://patents.google.com/patent/US7965111|US7965111B2]] |
| - | * S. Aniruddhan, B. Sun, A. Jayaraman and G.S. Sahota, "Mixer with High Output Power Accuracy and Low Local Oscillator Leakage", US 7,941,115, May 10, 2011. | + | * S. Aniruddhan, B. Sun, A. Jayaraman and G.S. Sahota, "Mixer with High Output Power Accuracy and Low Local Oscillator Leakage", US 7,941,115, May 10, 2011. [[https://patents.google.com/patent/US7941115|US7941115B2]] |
| - | * C. Narathong and S. Aniruddhan, "Techniques for improving Balun Loaded-Q", US 7,863,986, Jan. 4, 2011. | + | * C. Narathong and S. Aniruddhan, "Techniques for improving Balun Loaded-Q", US 7,863,986, Jan. 4, 2011. [[https://patents.google.com/patent/US20100033253|US20100033253A1]] |
| - | * Q. Khan, S. Wadhwa, D. Tripathi, G.K. Sidhartha, K. Misri, PVT Variation Detection and Compensation Circuit, US 7495465, Feb. 24, 2009. | + | * Q. Khan, S. Wadhwa, D. Tripathi, G.K. Sidhartha and K. Misri, "PVT Variation Detection and Compensation Circuit", US 7495465, Feb. 24, 2009. [[https://patents.google.com/patent/US7495465|US7495465B2]] |
| - | * D. Tripathi, G.K. Sidhartha, Q. Khan, K. Misri, S. Wadhwa, US 7446592, PVT Variation Detection and Compensation Circuit, Nov. 4, 2008. | + | * D. Tripathi, G.K. Sidhartha, Q. Khan, K. Misri and S. Wadhwa, "PVT Variation Detection and Compensation Circuit", US 7446592, Nov. 4, 2008. [[https://patents.google.com/patent/US7446592B2/en|US7446592B2]] |
| - | * Q. Khan, G.K. Sidhartha, Sequence-independent Power-on Reset for Multi-Voltage Circuits, US 7432748, Oct. 7, 2008. | + | * Q. Khan and G.K. Sidhartha, "Sequence-independent Power-on Reset for Multi-Voltage Circuits", US 7432748, Oct. 7, 2008. [[https://patents.google.com/patent/US7432748|US7432748B2]] |
| - | * D. Tripathi, J. Banerjee, Q. Khan, Differential Receiver Circuit, US 7414462, Aug. 19, 2008. | + | * D. Tripathi, J. Banerjee and Q. Khan, "Differential Receiver Circuit", US 7414462, Aug. 19, 2008. [[https://patents.google.com/patent/US7414462|US7414462B2]] |
| - | * Q. Khan, H. Fukazawa, T. Nandurkar, Charge Pump Circuit for High Side Drive Circuit and Driver Driving Voltage Circuit, US 7388422, Jun. 17, 2008. | + | * Q. Khan, H. Fukazawa and T. Nandurkar, "Charge Pump Circuit for High Side Drive Circuit and Driver Driving Voltage Circuit", US 7388422, Jun. 17, 2008. [[https://patents.google.com/patent/US7388422B2/en|US7388422B2]] |
| - | * G. K. Sidhartha, Q. Khan, D. Tripathi, S. Wadhwa, K. Misri, PVT Variation Detection and Compensation Circuit, US 7388419, Jun. 17, 2008. | + | * G. K. Sidhartha, Q. Khan, D. Tripathi, S. Wadhwa and K. Misri, "PVT Variation Detection and Compensation Circuit", US 7388419, Jun. 17, 2008. [[https://patents.google.com/patent/US7388419|US7388419B2]] |
| - | * N. Krishnapura(with I. Shpantzer et al.), "System and method for code division multiplexed optical communication", US 7,167,651, Jan. 23, 2007. | + | * Isaac Shpantzer, Michael Tseytlin, Yaakov Achiam, Aviv Salamon, Israel Smilanski, Olga Ritterbush, Pak Shing Cho, Li Guoliang, Jacob Khurgin, Yehouda Meiman, Alper Demir, Peter Feldman, Peter Kinget, Nagendra Krishnapura, Jaijeet Roychowdhury, Joseph Schwarzwalder and Charles Sciabarra, "System and method for code division multiplexed optical communication", US 7,167,651, Jan. 23, 2007. [[https://patents.google.com/patent/US7167651|US7167651B2]] |
| - | * Q. Khan, D. Tripathi, Transmission Line Driver Circuit, US 7292073, Nov. 6, 2007. | + | * Q. Khan and D. Tripathi, "Transmission Line Driver Circuit", US 7292073, Nov. 6, 2007. [[https://patents.google.com/patent/US7292073|US7292073B2]] |
| - | * D. Tripathi, Q. Khan, K. Misri, Transmission Line Driver, US 7187197, Mar. 6, 2007. | + | * D. Tripathi, Q. Khan and K. Misri, "Transmission Line Driver", US 7187197, Mar. 6, 2007. [[https://patents.google.com/patent/US7187197|US7187197B2]] |
| - | * S. Wadhwa, Q. Khan, K. Misri, D. Muhury, Digital Clock Frequency Doubler, US 7132863, Nov. 7, 2006. | + | * S. Wadhwa, Q. Khan, K. Misri and D. Muhury, "Digital Clock Frequency Doubler", US 7132863, Nov. 7, 2006. [[https://patents.google.com/patent/US7132863|US7132863B2]] |
| - | * Q. Khan, D. Tripathi, K. Misri, High Voltage Level Converter Using Low Voltage Devices, US 7102410, Sep. 5, 2006. | + | * Q. Khan, D. Tripathi and K. Misri, "High Voltage Level Converter Using Low Voltage Devices", US 7102410, Sep. 5, 2006. [[https://patents.google.com/patent/US7102410B2/en|US7102410B2]] |
| - | * Q. Khan, S. Wadhwa, K. Misri, Bandgap Reference Circuit, US 7084698, Aug. 1, 2006. | + | * Q. Khan, S. Wadhwa and K. Misri, "Bandgap Reference Circuit," US 7084698, Aug. 1, 2006. [[https://patents.google.com/patent/US7084698B2/en|US7084698B2]] |
| - | * Q. Khan, S. Wadhwa, K. Misri, Bidirectional Level Shifter, US 7061299, Jun, 13, 2006. | + | * Q. Khan, S. Wadhwa and K. Misri, "Bidirectional Level Shifter", US 7061299, Jun, 13, 2006. [[https://patents.google.com/patent/US7061299B2/en|US7061299B2]] |
| - | * Q. Khan, S. Wadhwa, K. Misri, Single Supply Level Shifter, US 7009424, Mar. 7, 2006. | + | * Q. Khan, S. Wadhwa and K. Misri, "Single Supply Level Shifter", US 7009424, Mar. 7, 2006. [[https://patents.google.com/patent/US7009424B2/en|US7009424B2]] |
| - | * Shanthi Pavan, "Integrated circuit implementation for power and area efficient adaptive equalization", US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California. | + | * Shanthi Pavan, "Integrated circuit implementation for power and area efficient adaptive equalization", US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California. [[https://patents.google.com/patent/US7142596|US7142596B2]] |
| - | * N. Krishnapura(with I. Shpantzer et al.), "System and method for orthogonal frequency division multiplexed optical communication", US 7,076,169, Jul. 11, 2006. | + | * Isaac Shpantzer, Yehouda Meiman, Michael Tseytlin, Olga Ritterbush, Aviv Salamon, Peter Feldman,Alper Demir,Peter Kinget, Nagendra Krishnapura and Jaijeet Roychowdhury, "System and method for orthogonal frequency division multiplexed optical communication", US 7,076,169, Jul. 11, 2006. [[https://patents.google.com/patent/US7076169|US7076169B2]] |
| - | * John S. Wang, Sudeep Bhoja, Shanthi Pavan, Hai Tao, "Method and apparatus for improved high-speed adaptive equalization", US 7,003,228, Feb. 21, 2006. | + | * John S. Wang, Sudeep Bhoja, Shanthi Pavan and Hai Tao, "Method and apparatus for improved high-speed adaptive equalization", US 7,003,228, Feb. 21, 2006. [[https://patents.google.com/patent/US7003228|US7003228B2]] |
| - | * Shanthi Pavan et al., "Mobility Compensation in MOS Integrated Circuits", US 6,822,505, 23 Nov. 2004. | + | * George Palaskas and Shanthi Y. Pavan, "Mobility Compensation in MOS Integrated Circuits", US 6,822,505, 23 Nov. 2004. [[https://patents.google.com/patent/US6822505B1/en|US6822505B1]] |
| - | * N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing", US 6,816,003, Nov. 9, 2004. | + | * N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing", US 6,816,003, Nov. 9, 2004. [[https://patents.google.com/patent/US6816003B2/en|US6816003B2]] |
| - | * N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing", US 6,717,461, Apr. 6, 2004. | + | * N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing", US 6,717,461, Apr. 6, 2004. [[https://patents.google.com/patent/US6717461B2/en|US6717461B2]] |
| - | * N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing", US 6,683,492, Jan. 27, 2004. | + | * N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing", US 6,683,492, Jan. 27, 2004. [[https://patents.google.com/patent/US6683492B2/en|US6683492B2]] |
| - | * P. Kinget and N. Krishnapura, "Glitch Free Phase Switching Synthesizer", US 6,671,341, Dec. 30, 2003. | + | * P. Kinget and N. Krishnapura, "Glitch Free Phase Switching Synthesizer", US 6,671,341, Dec. 30, 2003. [[https://patents.google.com/patent/US6671341B1/en|US6671341B1]] |
| - | * Shanthi Pavan et al., "Method and System for Compensation of Low-frequency Photodiode Current in a Transimpedance Amplifier", US 6,552,615, 22 Apr. 2003. | + | * Shanthi Pavan and Arvin Shahani, "Method and System for Compensation of Low-frequency Photodiode Current in a Transimpedance Amplifier", US 6,552,615, 22 Apr. 2003. [[https://patents.google.com/patent/US6552615B1/en|US6552615B1]] |
| - | * Shanthi Pavan et al., "Programmable Analog Tapped Delay Line Filter Having Cascaded Differential Delay Cells", US 6,545,567, 8 Apr. 2003. | + | * Shanthi Pavan, Sudeep Bhoja and John S. Wang, "Programmable Analog Tapped Delay Line Filter Having Cascaded Differential Delay Cells", US 6,545,567, 8 Apr. 2003. [[https://patents.google.com/patent/US6545567B1/en|US6545567B1]] |
| - | * Shanthi Pavan, "Fixed Transconductance Bias Apparatus", US 6,400,185, 4 Jun. 2002. | + | * Shanthi Pavan, "Fixed Transconductance Bias Apparatus", US 6,400,185, 4 Jun. 2002. [[https://patents.google.com/patent/US6400185B2/en|US6400185B2]] |
| - | * Shanthi Pavan et al., "Fast Acting Polarity Detector", US 6,369,726, 2 Apr. 2002. | + | * Krishnaswamy Nagaraj and Shanthi Y. Pavan, "Fast Acting Polarity Detector", US 6,369,726, 2 Apr. 2002. [[https://patents.google.com/patent/US6369726B1/en|US6369726B1]] |
| - | * Shanthi Pavan, "Low Distortion Sample-and-Hold Circuit", US 6,323,697, 27 Nov. 2001. | + | * Shanthi Pavan, "Low Distortion Sample-and-Hold Circuit", US 6,323,697, 27 Nov. 2001. [[https://patents.google.com/patent/US6323697B1/en|US6323697B1]] |
| - | * Shanthi Pavan, "High Frequency Boost Technique", US 6,304,134, 16 Oct. 2001 | + | * Shanthi Pavan, "High Frequency Boost Technique", US 6,304,134, 16 Oct. 2001. [[https://patents.google.com/patent/US6304134B1/en|US6304134B1]] |
| - | * P. Kinget and N. Krishnapura, "Programmable Frequency Divider", US 6,281,721, Aug. 28, 2001. | + | * P. Kinget and N. Krishnapura, "Programmable Frequency Divider", US 6,281,721, Aug. 28, 2001. [[https://patents.google.com/patent/US6281721B1/en|US6281721B1]] |
| - | * Shanthi Pavan et al., "Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation", US 5,945,889, 31 Aug. 1999. | + | * Yendluri Shanthi-Pavan, Krishnaswamy Nagaraj and Venugopal Gopinathan, "Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation", US 5,945,889, 31 Aug. 1999. [[https://patents.google.com/patent/US5945889A|US5945889A]] |