Integrated Circuits and Systems group, IIT Madras

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
Next revision Both sides next revision
publications:start [2020/03/22 13:51]
nagendra
publications:start [2020/03/28 18:51]
qkhan [2020]
Line 1: Line 1:
 +====== Publications ======
 +
  
 ===== 2020 ===== ===== 2020 =====
 +  * G. R., J. D. Bandarupalli,​ S. Saxena, "A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).
 +  * S. Mukherjee, A. Das, S. Seth, S. Saxena, "An energy-efficient 3Gb/S PAM4 full-duplex transmitter with 2-tap feed forward equalizer,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).
   * Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, Nagendra Krishnapura,​ "A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).   * Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, Nagendra Krishnapura,​ "A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).
   * Vipul Bajaj, Anand Kannan, Minkle Paul, Nagendra Krishnapura,​ "Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).   * Vipul Bajaj, Anand Kannan, Minkle Paul, Nagendra Krishnapura,​ "Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation).
 +  * A. D. Carmine, A. Santra, Q. Khan, "A current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation).
 +  * K. Peetala, A. Ranjan, R. Aenkamreddi,​ Q. Khan, "An Area Efficient, High-Resolution Fully Foldable Switched-Capacitor DC-DC Converter with 16% Efficiency Improvement,"​ //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation).
   * M. V. Praveen and N. Krishnapura,​ "High Linearity Transmit Power Mixers Using Baseband Current Feedback,"​ //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://​ieeexplore.ieee.org/​document/​8889460|doi:​ 10.1109/​JSSC.2019.2945962]]   * M. V. Praveen and N. Krishnapura,​ "High Linearity Transmit Power Mixers Using Baseband Current Feedback,"​ //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://​ieeexplore.ieee.org/​document/​8889460|doi:​ 10.1109/​JSSC.2019.2945962]]
  
Line 14: Line 20:
   * Raviteja Theertham and Shanthi Pavan, "​Unified analysis, modeling, and simulation of chopping artifacts in continuous-time delta-sigma converters,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 8, pp. 2831-2842, Aug. 2019. [[https://​ieeexplore.ieee.org/​document/​8698838|doi:​ 10.1109/​TCSI.2019.2907167]]   * Raviteja Theertham and Shanthi Pavan, "​Unified analysis, modeling, and simulation of chopping artifacts in continuous-time delta-sigma converters,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 8, pp. 2831-2842, Aug. 2019. [[https://​ieeexplore.ieee.org/​document/​8698838|doi:​ 10.1109/​TCSI.2019.2907167]]
   * Kishalay Dutta, Vinod Menezes and Shanthi Pavan, "​Analysis and design of cyclic switched-capacitor DC-DC converters,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 8, pp. 3227-3237, Aug. 2019. [[https://​ieeexplore.ieee.org/​document/​8698873|doi:​ 10.1109/​TCSI.2019.2907309]]   * Kishalay Dutta, Vinod Menezes and Shanthi Pavan, "​Analysis and design of cyclic switched-capacitor DC-DC converters,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 8, pp. 3227-3237, Aug. 2019. [[https://​ieeexplore.ieee.org/​document/​8698873|doi:​ 10.1109/​TCSI.2019.2907309]]
-  * Saravana Manivannan and Shanthi Pavan, "​Degradation of alias rejection in continuous-time bandpass delta-sigma converters due to weak loop filter nonlinearities,"​ //2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. [[https://​ieeexplore.ieee.org/​document/​8702763|doi:​ 10.1109/​ISCAS.2019.8702763]]+  * Saravana Manivannan and Shanthi Pavan, "​Degradation of alias rejection in continuous-time bandpass delta-sigma converters due to weak loop filter nonlinearities,"​ //2019 IEEE International Symposium on Circuits and Systems (ISCAS)//, Sapporo, Japan, 2019, pp. 1-5. [[https://​ieeexplore.ieee.org/​document/​8702763|doi:​ 10.1109/​ISCAS.2019.8702763]]
   * Shanthi Pavan, "​Simplified analysis of total integrated noise in passive switched-capacitor and N-path filters,"​ //2019 IEEE International Symposium on Circuits and Systems (ISCAS)//, Sapporo, Japan, 2019, pp. 1-5. [[https://​ieeexplore.ieee.org/​document/​8702129|doi:​ 10.1109/​ISCAS.2019.8702129]]   * Shanthi Pavan, "​Simplified analysis of total integrated noise in passive switched-capacitor and N-path filters,"​ //2019 IEEE International Symposium on Circuits and Systems (ISCAS)//, Sapporo, Japan, 2019, pp. 1-5. [[https://​ieeexplore.ieee.org/​document/​8702129|doi:​ 10.1109/​ISCAS.2019.8702129]]
   * Shanthi Pavan, "An alternative approach to Bode's Noise Theorem,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 5, pp. 738-742, May 2019. [[https://​ieeexplore.ieee.org/​document/​8675338|doi:​ 10.1109/​TCSII.2019.2907860]]   * Shanthi Pavan, "An alternative approach to Bode's Noise Theorem,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 5, pp. 738-742, May 2019. [[https://​ieeexplore.ieee.org/​document/​8675338|doi:​ 10.1109/​TCSII.2019.2907860]]
Line 26: Line 32:
   * Harikumar Ganesan, Boby George, Sankaran Aniruddhan and Saleem Haneefa, "A Dual Slope LVDT-to-Digital Converter,"​ //IEEE Sensors Journal//, vol. 19, no. 3, pp. 868-876, 1 Feb.1, 2019. [[https://​ieeexplore.ieee.org/​document/​8517138|doi:​ 10.1109/​JSEN.2018.2878883]]   * Harikumar Ganesan, Boby George, Sankaran Aniruddhan and Saleem Haneefa, "A Dual Slope LVDT-to-Digital Converter,"​ //IEEE Sensors Journal//, vol. 19, no. 3, pp. 868-876, 1 Feb.1, 2019. [[https://​ieeexplore.ieee.org/​document/​8517138|doi:​ 10.1109/​JSEN.2018.2878883]]
   * Anantha MS, Abhishek Kumar and Sankaran Aniruddhan, "A Compact +10/+5dBm 800/2600MHz LTE Driver Amplifier with Ground-Bounce Reduction,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 6, pp. 919-923, June 2019. [[https://​ieeexplore.ieee.org/​document/​8477034|doi:​ 10.1109/​TCSII.2018.2873053]]   * Anantha MS, Abhishek Kumar and Sankaran Aniruddhan, "A Compact +10/+5dBm 800/2600MHz LTE Driver Amplifier with Ground-Bounce Reduction,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 6, pp. 919-923, June 2019. [[https://​ieeexplore.ieee.org/​document/​8477034|doi:​ 10.1109/​TCSII.2018.2873053]]
-  * Arpan Thakkar, Srinivas Theertham and Sankaran Aniruddhan, "Phase Noise Analysis of Bipolar Class-C VCOs with Delay in Oscillator Loop," //IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 12, pp. 2873-2883, Dec. 2018. [[https://​ieeexplore.ieee.org/​document/​8471115|doi:​ 10.1109/​TVLSI.2018.2861818]]+  * Arpan Thakkar, Srinivas Theertham and Sankaran Aniruddhan, "Phase Noise Analysis of Bipolar Class-C VCOs with Delay in Oscillator Loop," //IEEE Transactions on Very Large Scale Integration (VLSI) Systems//, vol. 26, no. 12, pp. 2873-2883, Dec. 2018. [[https://​ieeexplore.ieee.org/​document/​8471115|doi:​ 10.1109/​TVLSI.2018.2861818]]
   * Ahmad Sharkia, Sankaran Aniruddhan, Shahriar Mirabbasi and Sudip Shekhar, "A Compact, Voltage-Mode Type-I PLL with Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 1, pp. 43-53, Jan. 2019. [[https://​ieeexplore.ieee.org/​document/​8432060|doi:​ 10.1109/​TCSI.2018.2858197]]   * Ahmad Sharkia, Sankaran Aniruddhan, Shahriar Mirabbasi and Sudip Shekhar, "A Compact, Voltage-Mode Type-I PLL with Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 66, no. 1, pp. 43-53, Jan. 2019. [[https://​ieeexplore.ieee.org/​document/​8432060|doi:​ 10.1109/​TCSI.2018.2858197]]
-  * G. Vinodhini, Boby George, Sankaran Aniruddhan, J. Dhurga Devi and P.V. Ramakrishna,​ "​Performance Analysis of Oscillator Based Read-out Circuit for LVDT," //IEEE Transactions on Instrumentation and Measurement,​ vol. 68, no. 4, pp. 1080-1088, April 2019. [[https://​ieeexplore.ieee.org/​document/​8434261|doi:​ 10.1109/​TIM.2018.2858038]]+  * G. Vinodhini, Boby George, Sankaran Aniruddhan, J. Dhurga Devi and P.V. Ramakrishna,​ "​Performance Analysis of Oscillator Based Read-out Circuit for LVDT," //IEEE Transactions on Instrumentation and Measurement//, vol. 68, no. 4, pp. 1080-1088, April 2019. [[https://​ieeexplore.ieee.org/​document/​8434261|doi:​ 10.1109/​TIM.2018.2858038]]
   * R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura,​ "​Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 11, pp. 3651-3661, Nov. 2018. [[https://​ieeexplore.ieee.org/​document/​8428537|doi:​ 10.1109/​TCSI.2018.2854707]]   * R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura,​ "​Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 65, no. 11, pp. 3651-3661, Nov. 2018. [[https://​ieeexplore.ieee.org/​document/​8428537|doi:​ 10.1109/​TCSI.2018.2854707]]
   * Abhishek Bhat and Nagendra Krishnapura,​ "​On-Chip Static Phase Difference Measurement Circuit with Gain and Offset Calibration,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 2, pp. 162-166, Feb. 2019. [[https://​ieeexplore.ieee.org/​document/​8369120|doi:​ 10.1109/​TCSII.2018.2842101]]   * Abhishek Bhat and Nagendra Krishnapura,​ "​On-Chip Static Phase Difference Measurement Circuit with Gain and Offset Calibration,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 66, no. 2, pp. 162-166, Feb. 2019. [[https://​ieeexplore.ieee.org/​document/​8369120|doi:​ 10.1109/​TCSII.2018.2842101]]
Line 88: Line 94:
   * S. Pavan and N. Krishnapura,​ "​Demystifying Time Varying Circuits and Systems,"​ //2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)//, Kolkata, 2016, pp. 17-18. [[https://​ieeexplore.ieee.org/​document/​7434912|doi:​ 10.1109/​VLSID.2016.135]]   * S. Pavan and N. Krishnapura,​ "​Demystifying Time Varying Circuits and Systems,"​ //2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)//, Kolkata, 2016, pp. 17-18. [[https://​ieeexplore.ieee.org/​document/​7434912|doi:​ 10.1109/​VLSID.2016.135]]
   * R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu, "A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 64, no. 2, pp. 283-295, Feb. 2017. [[https://​ieeexplore.ieee.org/​document/​7731190|doi:​ 10.1109/​TCSI.2016.2609855]]   * R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu, "A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 64, no. 2, pp. 283-295, Feb. 2017. [[https://​ieeexplore.ieee.org/​document/​7731190|doi:​ 10.1109/​TCSI.2016.2609855]]
-  * A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, "A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,"​ //IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1771-1784, Aug. 2016. [[https://​ieeexplore.ieee.org/​document/​7489022|doi:​ 10.1109/​JSSC.2016.2557807]]+  * A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, "A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,"​ //IEEE Journal of Solid-State Circuits//, vol. 51, no. 8, pp. 1771-1784, Aug. 2016. [[https://​ieeexplore.ieee.org/​document/​7489022|doi:​ 10.1109/​JSSC.2016.2557807]]
   * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, "A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition,"​ //IEEE Journal of Solid-State Circuits//, vol. 51, no. 2, pp. 428-439, Feb. 2016. [[https://​ieeexplore.ieee.org/​document/​7362125|doi:​ 10.1109/​JSSC.2015.2497963]]   * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, "A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition,"​ //IEEE Journal of Solid-State Circuits//, vol. 51, no. 2, pp. 428-439, Feb. 2016. [[https://​ieeexplore.ieee.org/​document/​7362125|doi:​ 10.1109/​JSSC.2015.2497963]]
   * G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar,​ R. Nandwana, and P. K. Hanumolu, "23.1 A 16Mb/​s-to-8Gb/​s 14.1-to-5.9pJ/​b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS," //2016 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2016, pp. 398-399. [[https://​ieeexplore.ieee.org/​document/​7418075|doi:​ 10.1109/​ISSCC.2016.7418075]]   * G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar,​ R. Nandwana, and P. K. Hanumolu, "23.1 A 16Mb/​s-to-8Gb/​s 14.1-to-5.9pJ/​b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS," //2016 IEEE International Solid-State Circuits Conference (ISSCC)//, San Francisco, CA, 2016, pp. 398-399. [[https://​ieeexplore.ieee.org/​document/​7418075|doi:​ 10.1109/​ISSCC.2016.7418075]]
Line 103: Line 109:
   *  R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar,​ A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, "A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/​Current-Mode Phase Interpolation Method,"​ //IEEE Journal of Solid-State Circuits//, vol. 50, no. 4, pp. 882-895, April 2015. [[https://​ieeexplore.ieee.org/​document/​7029717|doi:​ 10.1109/​JSSC.2014.2385756]]   *  R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar,​ A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, "A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/​Current-Mode Phase Interpolation Method,"​ //IEEE Journal of Solid-State Circuits//, vol. 50, no. 4, pp. 882-895, April 2015. [[https://​ieeexplore.ieee.org/​document/​7029717|doi:​ 10.1109/​JSSC.2014.2385756]]
   * A. Elkholy, S. Saxena, and P. K. Hanumolu, "A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter,"​ //2015 IEEE Custom Integrated Circuits Conference (CICC)//, San Jose, CA, 2015, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​7338376|doi:​ 10.1109/​CICC.2015.7338376]]   * A. Elkholy, S. Saxena, and P. K. Hanumolu, "A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter,"​ //2015 IEEE Custom Integrated Circuits Conference (CICC)//, San Jose, CA, 2015, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​7338376|doi:​ 10.1109/​CICC.2015.7338376]]
-  * S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar,​ A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choiand P. K. Hanumolu, "A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS," //2015 Symposium on VLSI Circuits (VLSI Circuits)//,​ Kyoto, 2015, pp. C352-C353. [[https://​ieeexplore.ieee.org/​document/​7231320|doi:​ 10.1109/​VLSIC.2015.7231320]] +  * S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar,​ A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi and P. K. Hanumolu, "A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS," //2015 Symposium on VLSI Circuits (VLSI Circuits)//,​ Kyoto, 2015, pp. C352-C353. [[https://​ieeexplore.ieee.org/​document/​7231320|doi:​ 10.1109/​VLSIC.2015.7231320]] 
-  * T. Anand, M. Talegaonkar,​ A. Elkholy, S. Saxena, A. Elshazlyand P. K. Hanumolu, "3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS," //2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers//, San Francisco, CA, 2015, pp. 1-3. [[https://​ieeexplore.ieee.org/​document/​7062927|doi:​ 10.1109/​ISSCC.2015.7062927]]+  * T. Anand, M. Talegaonkar,​ A. Elkholy, S. Saxena, A. Elshazly and P. K. Hanumolu, "3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS," //2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers//, San Francisco, CA, 2015, pp. 1-3. [[https://​ieeexplore.ieee.org/​document/​7062927|doi:​ 10.1109/​ISSCC.2015.7062927]]
   * S. J. Kim, R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski,​ and P. K. Hanumolu, “A 4-phase 30-70 MHz switching frequency buck converter using a time-based compensator,​” //IEEE Journal of Solid-State Circuits//, vol. 50, no. 12, pp. 2814-2824, Dec. 2015. [[https://​ieeexplore.ieee.org/​document/​7182789|doi:​ 10.1109/​JSSC.2015.2456884]]   * S. J. Kim, R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski,​ and P. K. Hanumolu, “A 4-phase 30-70 MHz switching frequency buck converter using a time-based compensator,​” //IEEE Journal of Solid-State Circuits//, vol. 50, no. 12, pp. 2814-2824, Dec. 2015. [[https://​ieeexplore.ieee.org/​document/​7182789|doi:​ 10.1109/​JSSC.2015.2456884]]
-  * S. J. Kim, Q. Khan, M. Talegaonkar,​ A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyreand P. K. Hanumolu, “High Frequency Buck Converter Design Using Time-Based Control Techniques,"​ //IEEE Journal of Solid-State Circuits//, vol. 50, no. 4, pp. 990-1001, April 2015. [[https://​ieeexplore.ieee.org/​document/​6998097|doi:​ 10.1109/​JSSC.2014.2378216]] +  * S. J. Kim, Q. Khan, M. Talegaonkar,​ A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre and P. K. Hanumolu, “High Frequency Buck Converter Design Using Time-Based Control Techniques,"​ //IEEE Journal of Solid-State Circuits//, vol. 50, no. 4, pp. 990-1001, April 2015. [[https://​ieeexplore.ieee.org/​document/​6998097|doi:​ 10.1109/​JSSC.2014.2378216]] 
-  * S. J. Kim; R. K. Nandwana, Q. Khan, R. Pilawa-PodgurskiP. K. Hanumolu, “12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS," //2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers//, San Francisco, CA, 2015, pp. 1-3. [[https://​ieeexplore.ieee.org/​document/​7063003|doi:​ 10.1109/​ISSCC.2015.7063003]]+  * S. J. Kim; R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski ​and P. K. Hanumolu, “12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS," //2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers//, San Francisco, CA, 2015, pp. 1-3. [[https://​ieeexplore.ieee.org/​document/​7063003|doi:​ 10.1109/​ISSCC.2015.7063003]]
  
  
Line 119: Line 125:
   * N. Rajesh and S.Pavan, "​Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming,"​ //IEEE Journal of Solid-State Circuits//, vol. 49, no. 8, pp. 1800-1814, Aug. 2014. [[https://​ieeexplore.ieee.org/​document/​6809227|doi:​ 10.1109/​JSSC.2014.2317132]]   * N. Rajesh and S.Pavan, "​Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming,"​ //IEEE Journal of Solid-State Circuits//, vol. 49, no. 8, pp. 1800-1814, Aug. 2014. [[https://​ieeexplore.ieee.org/​document/​6809227|doi:​ 10.1109/​JSSC.2014.2317132]]
   * Abhishek Kumar, S. Aniruddhan and Radha Krishna Ganti, "​Directional coupler with high isolation bandwidth using electrical balance,"​ //2014 IEEE MTT-S International Microwave Symposium (IMS2014)//,​ Tampa, FL, 2014, pp. 1-3. [[https://​ieeexplore.ieee.org/​document/​6848434|doi:​ 10.1109/​MWSYM.2014.6848434]] ​   * Abhishek Kumar, S. Aniruddhan and Radha Krishna Ganti, "​Directional coupler with high isolation bandwidth using electrical balance,"​ //2014 IEEE MTT-S International Microwave Symposium (IMS2014)//,​ Tampa, FL, 2014, pp. 1-3. [[https://​ieeexplore.ieee.org/​document/​6848434|doi:​ 10.1109/​MWSYM.2014.6848434]] ​
-  * Saravanan Kand S. Aniruddhan, "​Replica bias scheme for efficient power utilization in high-frequency CMOS digital circuits,"​ //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 1002-1005. [[https://​ieeexplore.ieee.org/​document/​6865307|doi:​ 10.1109/​ISCAS.2014.6865307]]+  * Saravanan K and S. Aniruddhan, "​Replica bias scheme for efficient power utilization in high-frequency CMOS digital circuits,"​ //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 1002-1005. [[https://​ieeexplore.ieee.org/​document/​6865307|doi:​ 10.1109/​ISCAS.2014.6865307]]
   * Abhishek Kumar and S. Aniruddhan, "​Ground-Bounce Reduction in Narrow-Band RF Front-Ends,"​ //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 189-192. [[https://​ieeexplore.ieee.org/​document/​6865097|doi:​ 10.1109/​ISCAS.2014.6865097]]   * Abhishek Kumar and S. Aniruddhan, "​Ground-Bounce Reduction in Narrow-Band RF Front-Ends,"​ //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 189-192. [[https://​ieeexplore.ieee.org/​document/​6865097|doi:​ 10.1109/​ISCAS.2014.6865097]]
   * Gaurav Agrawal, S. Aniruddhan and Radha Krishna Ganti, "​Multi-band RF time delay element based on frequency translation,"​ //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 1368-1371. [[https://​ieeexplore.ieee.org/​document/​6865398|doi:​ 10.1109/​ISCAS.2014.6865398]]   * Gaurav Agrawal, S. Aniruddhan and Radha Krishna Ganti, "​Multi-band RF time delay element based on frequency translation,"​ //2014 IEEE International Symposium on Circuits and Systems (ISCAS)//, Melbourne VIC, 2014, pp. 1368-1371. [[https://​ieeexplore.ieee.org/​document/​6865398|doi:​ 10.1109/​ISCAS.2014.6865398]]
Line 128: Line 134:
   * N. Krishnapura,​ "​Tutorial T6A: Pedagogy of Negative Feedback Circuits,"​ //2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems//, Mumbai, 2014, pp. 13-13. [[https://​ieeexplore.ieee.org/​document/​6733095|doi:​ 10.1109/​VLSID.2014.121]]   * N. Krishnapura,​ "​Tutorial T6A: Pedagogy of Negative Feedback Circuits,"​ //2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems//, Mumbai, 2014, pp. 13-13. [[https://​ieeexplore.ieee.org/​document/​6733095|doi:​ 10.1109/​VLSID.2014.121]]
   * S. Saxena, R. K. Nandwana and P. K. Hanumolu, "A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis,"​ //IEEE Journal of Solid-State Circuits//, vol. 49, no. 8, pp. 1827-1836, Aug. 2014. [[https://​ieeexplore.ieee.org/​document/​6809856|doi:​ 10.1109/​JSSC.2014.2317142]]   * S. Saxena, R. K. Nandwana and P. K. Hanumolu, "A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis,"​ //IEEE Journal of Solid-State Circuits//, vol. 49, no. 8, pp. 1827-1836, Aug. 2014. [[https://​ieeexplore.ieee.org/​document/​6809856|doi:​ 10.1109/​JSSC.2014.2317142]]
-  * G. Shu, S. Saxena, W. -S. Choi, M. Talegaonkar,​ A. Elshazly, B. Youngand P. K. Hanumolu, "A reference-less clock and data recovery circuit using phase-rotating phase-locked loop," //IEEE Journal of Solid-State Circuits//, vol. 49, no. 4, pp. 1036-1047, April 2014. [[https://​ieeexplore.ieee.org/​document/​6712167|doi:​ 10.1109/​JSSC.2013.2296152]] +  * G. Shu, S. Saxena, W. -S. Choi, M. Talegaonkar,​ A. Elshazly, B. Young and P. K. Hanumolu, "A reference-less clock and data recovery circuit using phase-rotating phase-locked loop," //IEEE Journal of Solid-State Circuits//, vol. 49, no. 4, pp. 1036-1047, April 2014. [[https://​ieeexplore.ieee.org/​document/​6712167|doi:​ 10.1109/​JSSC.2013.2296152]] 
-  * R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar,​ A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, "A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/​current-mode phase interpolator with 13.2dB phase noise improvement,"​ //2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, 2014, pp. 1-2. [[https://​ieeexplore.ieee.org/​document/​6858446|doi:​ 10.1109/​VLSIC.2014.6858446]] +  * R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar,​ A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, "A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/​current-mode phase interpolator with 13.2dB phase noise improvement,"​ //2014 Symposium on VLSI Circuits Digest of Technical Papers//, Honolulu, HI, 2014, pp. 1-2. [[https://​ieeexplore.ieee.org/​document/​6858446|doi:​ 10.1109/​VLSIC.2014.6858446]] 
-  * M. Talegaonkar,​ T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choiand P. K. Hanumolu, "A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter,"​ //2014 Symposium on VLSI Circuits Digest of Technical Papers//, Honolulu, HI, 2014, pp. 1-2. [[https://​ieeexplore.ieee.org/​document/​6858392|doi:​ 10.1109/​VLSIC.2014.6858392]] +  * M. Talegaonkar,​ T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choi and P. K. Hanumolu, "A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter,"​ //2014 Symposium on VLSI Circuits Digest of Technical Papers//, Honolulu, HI, 2014, pp. 1-2. [[https://​ieeexplore.ieee.org/​document/​6858392|doi:​ 10.1109/​VLSIC.2014.6858392]] 
-  * A. Elkholy, A. Elshazly, S. Saxena, G. Shuand P. K. Hanumolu, "15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS," //2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)//, San Francisco, CA, 2014, pp. 272-273. [[https://​ieeexplore.ieee.org/​document/​6757431|doi:​ 10.1109/​ISSCC.2014.6757431]] +  * A. Elkholy, A. Elshazly, S. Saxena, G. Shu and P. K. Hanumolu, "15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS," //2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)//, San Francisco, CA, 2014, pp. 272-273. [[https://​ieeexplore.ieee.org/​document/​6757431|doi:​ 10.1109/​ISSCC.2014.6757431]] 
-  * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazlyand P. K. Hanumolu, "8.7 A 4-to-10.5Gb/​s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS," //2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)//, San Francisco, CA, 2014, pp. 150-151. [[https://​ieeexplore.ieee.org/​document/​6757377|doi:​ 10.1109/​ISSCC.2014.6757377]]+  * G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly and P. K. Hanumolu, "8.7 A 4-to-10.5Gb/​s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS," //2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)//, San Francisco, CA, 2014, pp. 150-151. [[https://​ieeexplore.ieee.org/​document/​6757377|doi:​ 10.1109/​ISSCC.2014.6757377]]
   * Q. Khan, S. J. Kim; M. Talegaonkar,​ A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre and P. K. Hanumolu, “A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW," //2014 Symposium on VLSI Circuits Digest of Technical Papers//, Honolulu, HI, 2014, pp. 1-2. [[https://​ieeexplore.ieee.org/​document/​6858439|doi:​ 10.1109/​VLSIC.2014.6858439]]   * Q. Khan, S. J. Kim; M. Talegaonkar,​ A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre and P. K. Hanumolu, “A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW," //2014 Symposium on VLSI Circuits Digest of Technical Papers//, Honolulu, HI, 2014, pp. 1-2. [[https://​ieeexplore.ieee.org/​document/​6858439|doi:​ 10.1109/​VLSIC.2014.6858439]]
  
 ===== 2013 ===== ===== 2013 =====
-  * Janakiraman V., Pandharpure S.J. and Watts J., (2014) "​Statistical Compact Model Extraction for Skewed Gaussian Variations"​In: Jain V., Verma A. (eds) Physics of Semiconductor Devices. Environmental Science and Engineering. Springer, Cham. [[https://​link.springer.com/​chapter/​10.1007%2F978-3-319-03002-9_51|paper]]+  * Janakiraman V., Pandharpure S.J. and Watts J., (2014) "​Statistical Compact Model Extraction for Skewed Gaussian Variations"​, "In: Jain V., Verma A. (eds) Physics of Semiconductor Devices. Environmental Science and Engineering". Springer, Cham. [[https://​link.springer.com/​chapter/​10.1007%2F978-3-319-03002-9_51|paper]]
   * S. Pavan, "​Systematic Derivation of Well Known Analog Circuits,"​ //2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)//,​ Visakhapatnam,​ 2013, pp. 1-12. [[https://​ieeexplore.ieee.org/​document/​6731167|doi:​ 10.1109/​PrimeAsia.2013.6731167]]   * S. Pavan, "​Systematic Derivation of Well Known Analog Circuits,"​ //2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)//,​ Visakhapatnam,​ 2013, pp. 1-12. [[https://​ieeexplore.ieee.org/​document/​6731167|doi:​ 10.1109/​PrimeAsia.2013.6731167]]
   * M.Veeramani,​ P.Shyam, N.Ratchagar,​A.Chadha,​ E.Bhattacharya and S.Pavan, "​Compact silicon biosensor for the clinical range estimation of blood serum triglycéride,"​ //SENSORS, 2013 IEEE//, Baltimore, MD, 2013, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​6688212|doi:​ 10.1109/​ICSENS.2013.6688212]] ​     * M.Veeramani,​ P.Shyam, N.Ratchagar,​A.Chadha,​ E.Bhattacharya and S.Pavan, "​Compact silicon biosensor for the clinical range estimation of blood serum triglycéride,"​ //SENSORS, 2013 IEEE//, Baltimore, MD, 2013, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​6688212|doi:​ 10.1109/​ICSENS.2013.6688212]] ​  
Line 146: Line 152:
   * M.Veeramani,​ P.Shyam, N.Ratchagar,​A.Chadha,​ E.Bhattacharya and S.Pavan, "A Miniaturized pH Sensor With an Embedded Counter Electrode and a Readout Circuit",​ //IEEE Sensors Journal//, vol. 13, no. 5, pp. 1941-1948, May 2013. [[https://​ieeexplore.ieee.org/​document/​6428589|doi:​ 10.1109/​JSEN.2013.2245032]]   * M.Veeramani,​ P.Shyam, N.Ratchagar,​A.Chadha,​ E.Bhattacharya and S.Pavan, "A Miniaturized pH Sensor With an Embedded Counter Electrode and a Readout Circuit",​ //IEEE Sensors Journal//, vol. 13, no. 5, pp. 1941-1948, May 2013. [[https://​ieeexplore.ieee.org/​document/​6428589|doi:​ 10.1109/​JSEN.2013.2245032]]
   * A. Jain and S. Pavan, "​Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface,"​ //2013 IEEE International Symposium on Circuits and Systems (ISCAS)//, Beijing, 2013, pp. 1252-1255. [[https://​ieeexplore.ieee.org/​document/​6572080|doi:​ 10.1109/​ISCAS.2013.6572080]]   * A. Jain and S. Pavan, "​Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface,"​ //2013 IEEE International Symposium on Circuits and Systems (ISCAS)//, Beijing, 2013, pp. 1252-1255. [[https://​ieeexplore.ieee.org/​document/​6572080|doi:​ 10.1109/​ISCAS.2013.6572080]]
-  * S. Pavan, "A Time Domain Perspective of the Signal Transfer Function of a Continuous-time Delta Sigma Modulator,"​ // IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 60, no. 2, pp. 81-85, Feb. 2013 [[https://​ieeexplore.ieee.org/​document/​6477097|doi:​ 10.1109/​TCSII.2012.2235016]] +  * S. Pavan, "A Time Domain Perspective of the Signal Transfer Function of a Continuous-time Delta Sigma Modulator,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 60, no. 2, pp. 81-85, Feb. 2013 [[https://​ieeexplore.ieee.org/​document/​6477097|doi:​ 10.1109/​TCSII.2012.2235016]] 
-  * S. Pavan, "​Simulation Techniques in Data Converter Design,"​ // Tutorial at the International Solid State Circuits Conference (ISSCC) //, February 2013. [[https://​resourcecenter.sscs.ieee.org/​short-courses-and-tutorials/​2013-isscc-short-courses-and-tutorials/​SSCSTUT20130102.html|paper]] +  * S. Pavan, "​Simulation Techniques in Data Converter Design,"​ //Tutorial at the International Solid State Circuits Conference (ISSCC)//, February 2013. [[https://​resourcecenter.sscs.ieee.org/​short-courses-and-tutorials/​2013-isscc-short-courses-and-tutorials/​SSCSTUT20130102.html|paper]] 
-  * S. Saxena, R. K. Nandwanaand P. K. Hanumolu, "A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter,"​ //​Proceedings of the IEEE 2013 Custom Integrated Circuits Conference//,​ San Jose, CA, 2013, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​6658403|doi:​ 10.1109/​CICC.2013.6658403]] +  * S. Saxena, R. K. Nandwana and P. K. Hanumolu, "A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter,"​ //​Proceedings of the IEEE 2013 Custom Integrated Circuits Conference//,​ San Jose, CA, 2013, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​6658403|doi:​ 10.1109/​CICC.2013.6658403]] 
-  *  R. K. Nandwana, S. Saxenaand P. K. Hanumolu, "A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC," //2013 Symposium on VLSI Circuits//, Kyoto, 2013, pp. C156-C157. [[https://​ieeexplore.ieee.org/​document/​6578645|paper]]+  *  R. K. Nandwana, S. Saxena and P. K. Hanumolu, "A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC," //2013 Symposium on VLSI Circuits//, Kyoto, 2013, pp. C156-C157. [[https://​ieeexplore.ieee.org/​document/​6578645|paper]]
   * G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar,​ R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu,"​A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR," //2013 Symposium on VLSI Circuits//, Kyoto, 2013, pp. C278-C279. [[https://​ieeexplore.ieee.org/​document/​6578694|paper]]   * G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar,​ R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu,"​A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR," //2013 Symposium on VLSI Circuits//, Kyoto, 2013, pp. C278-C279. [[https://​ieeexplore.ieee.org/​document/​6578694|paper]]
  
Line 155: Line 161:
  
 ===== 2012 =====  ​ ===== 2012 =====  ​
-  * Janakiraman Viraraghavan,​ Shrinivas J. PandharpureJosef Watts, "​Statistical Compact Model Extraction: A Neural Network Approach,"​ //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems//, vol. 31, no. 12, pp. 1920-1924, Dec. 2012. [[https://​ieeexplore.ieee.org/​document/​6349439|doi:​ 10.1109/​TCAD.2012.2207955]]+  * Janakiraman Viraraghavan,​ Shrinivas J. Pandharpure ​and Josef Watts, "​Statistical Compact Model Extraction: A Neural Network Approach,"​ //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems//, vol. 31, no. 12, pp. 1920-1924, Dec. 2012. [[https://​ieeexplore.ieee.org/​document/​6349439|doi:​ 10.1109/​TCAD.2012.2207955]]
   * P. Shettigar and S.Pavan, "​Design Techniques for Wideband Continuous-time Delta-Sigma Modulators with FIR Feedback DACs," //IEEE Journal of Solid-State Circuits//, vol. 47, no. 12, pp. 2865-2879, Dec. 2012. [[https://​ieeexplore.ieee.org/​document/​6341855|doi:​ 10.1109/​JSSC.2012.2217871]]   * P. Shettigar and S.Pavan, "​Design Techniques for Wideband Continuous-time Delta-Sigma Modulators with FIR Feedback DACs," //IEEE Journal of Solid-State Circuits//, vol. 47, no. 12, pp. 2865-2879, Dec. 2012. [[https://​ieeexplore.ieee.org/​document/​6341855|doi:​ 10.1109/​JSSC.2012.2217871]]
   * T. Nandi, K. Boominathan and S.Pavan, " A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC," //​Proceedings of the IEEE 2012 Custom Integrated Circuits Conference//,​ San Jose, CA, 2012, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​6330692|doi:​ 10.1109/​CICC.2012.6330692]]   * T. Nandi, K. Boominathan and S.Pavan, " A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC," //​Proceedings of the IEEE 2012 Custom Integrated Circuits Conference//,​ San Jose, CA, 2012, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​6330692|doi:​ 10.1109/​CICC.2012.6330692]]
Line 166: Line 172:
   * Sankaran Aniruddhan, "​Quadrature generation techniques in CMOS relaxation oscillators,"​ //2012 IEEE International Symposium on Circuits and Systems (ISCAS)//, Seoul, 2012, pp. 1375-1378. [[https://​ieeexplore.ieee.org/​document/​6271499|doi:​ 10.1109/​ISCAS.2012.6271499]]   * Sankaran Aniruddhan, "​Quadrature generation techniques in CMOS relaxation oscillators,"​ //2012 IEEE International Symposium on Circuits and Systems (ISCAS)//, Seoul, 2012, pp. 1375-1378. [[https://​ieeexplore.ieee.org/​document/​6271499|doi:​ 10.1109/​ISCAS.2012.6271499]]
   * P. Shettigar and S.Pavan, "A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS," //2012 IEEE International Solid-State Circuits Conference//,​ San Francisco, CA, 2012, pp. 156-158. **(Winner of the ISSCC 2012 Silk Road Award)** [[https://​ieeexplore.ieee.org/​document/​6176957|doi:​ 10.1109/​ISSCC.2012.6176957]]   * P. Shettigar and S.Pavan, "A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS," //2012 IEEE International Solid-State Circuits Conference//,​ San Francisco, CA, 2012, pp. 156-158. **(Winner of the ISSCC 2012 Silk Road Award)** [[https://​ieeexplore.ieee.org/​document/​6176957|doi:​ 10.1109/​ISSCC.2012.6176957]]
-  * R. Zanbaghi, S. Saxena, G. C. Temesand T. S. Fiez, "A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 59, no. 8, pp. 1614-1625, Aug. 2012. [[https://​ieeexplore.ieee.org/​abstract/​document/​6243236|doi:​ 10.1109/​TCSI.2012.2206509]] +  * R. Zanbaghi, S. Saxena, G. C. Temes and T. S. Fiez, "A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 59, no. 8, pp. 1614-1625, Aug. 2012. [[https://​ieeexplore.ieee.org/​abstract/​document/​6243236|doi:​ 10.1109/​TCSI.2012.2206509]] 
-  * S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaramand T. S. Fiez, "A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 59, no. 8, pp. 1604-1613, Aug. 2012. [[https://​ieeexplore.ieee.org/​abstract/​document/​6243235|doi:​ 10.1109/​TCSI.2012.2206506]]+  * S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram and T. S. Fiez, "A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 59, no. 8, pp. 1604-1613, Aug. 2012. [[https://​ieeexplore.ieee.org/​abstract/​document/​6243235|doi:​ 10.1109/​TCSI.2012.2206506]]
   * Q. Khan, A. Elshazly, S. Rao,R. Inti and P. K. Hanumolu, “A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control,"​ //2012 Symposium on VLSI Circuits (VLSIC)//, Honolulu, HI, 2012, pp. 182-183. [[https://​ieeexplore.ieee.org/​document/​6243850|doi:​ 10.1109/​VLSIC.2012.6243850]]   * Q. Khan, A. Elshazly, S. Rao,R. Inti and P. K. Hanumolu, “A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control,"​ //2012 Symposium on VLSI Circuits (VLSIC)//, Honolulu, HI, 2012, pp. 182-183. [[https://​ieeexplore.ieee.org/​document/​6243850|doi:​ 10.1109/​VLSIC.2012.6243850]]
  
 ===== 2011 ===== ===== 2011 =====
-  * Janakiraman Viraraghavan,​ Shrinivas J. Pandharpure,​ Josef Watts, "​Statistical Compact Model Extraction: A Neural Network Approach, International Workshop on Physics of Semiconductor Devices, 2011 [**Poster**] [[https://​aml.ece.iisc.ac.in/​images/​2/​2c/​Statistical-Modeling.pdf|poster]] +  * Janakiraman Viraraghavan,​ Shrinivas J. Pandharpure,​ Josef Watts, "​Statistical Compact Model Extraction: A Neural Network Approach, ​//International Workshop on Physics of Semiconductor Devices//, 2011 [**Poster**] [[https://​aml.ece.iisc.ac.in/​images/​2/​2c/​Statistical-Modeling.pdf|poster]] 
-  * Vikas Singh, Nagendra Krishnapura,​ Shanthi Pavan, Baradwaj Vigraham, Nimit NiganiaDebasish Behera, "A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay,"​ //​Proceedings of the 2011 IEEE Custom Integrated Circuits Conference//,​ San Jose, September 2011. [[https://​ieeexplore.ieee.org/​document/​6220855|doi:​ 10.1109/​JSSC.2012.2196730]] +  * Vikas Singh, Nagendra Krishnapura,​ Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania ​and Debasish Behera, "A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay,"​ //​Proceedings of the 2011 IEEE Custom Integrated Circuits Conference//,​ San Jose, September 2011. [[https://​ieeexplore.ieee.org/​document/​6220855|doi:​ 10.1109/​JSSC.2012.2196730]] 
-  * A. Jain, M. Venkatesan and S. Pavan, "A 4mW 1GS/S Continuous-Time DeltaSigma Modulator with 15.6MHz Bandwidth and 67dB Dynamic Range" //2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, 2011, pp. 259-262. [[https://​ieeexplore.ieee.org/​document/​6044956|doi:​ 10.1109/​ESSCIRC.2011.6044956]]+  * A. Jain, M. Venkatesan and S. Pavan, "A 4mW 1GS/S Continuous-Time DeltaSigma Modulator with 15.6MHz Bandwidth and 67dB Dynamic Range" //2011 Proceedings of the ESSCIRC (ESSCIRC)//, Helsinki, 2011, pp. 259-262. [[https://​ieeexplore.ieee.org/​document/​6044956|doi:​ 10.1109/​ESSCIRC.2011.6044956]]
   * S. Thyagarajan,​ S. Pavan and P. Sankar, "​Active-RC Filters Using the Gm-Assisted OTA-RC Technique,"​ //IEEE Journal of Solid-State Circuits//, vol. 46, no. 7, pp. 1522-1533, July 2011. [[https://​ieeexplore.ieee.org/​document/​5765707|doi:​ 10.1109/​JSSC.2011.2143590]]   * S. Thyagarajan,​ S. Pavan and P. Sankar, "​Active-RC Filters Using the Gm-Assisted OTA-RC Technique,"​ //IEEE Journal of Solid-State Circuits//, vol. 46, no. 7, pp. 1522-1533, July 2011. [[https://​ieeexplore.ieee.org/​document/​5765707|doi:​ 10.1109/​JSSC.2011.2143590]]
   * Chembiyan Thambidurai and Nagendra Krishnapura,​ "On Pulse Position Modulation and Its Application to PLLs for Spur Reduction,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 58, no. 7, pp. 1483-1496, July 2011. [[https://​ieeexplore.ieee.org/​document/​5892914|doi:​ 10.1109/​TCSI.2011.2157749]]   * Chembiyan Thambidurai and Nagendra Krishnapura,​ "On Pulse Position Modulation and Its Application to PLLs for Spur Reduction,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 58, no. 7, pp. 1483-1496, July 2011. [[https://​ieeexplore.ieee.org/​document/​5892914|doi:​ 10.1109/​TCSI.2011.2157749]]
   * S. Aniruddhan, Sudip Shekhar and David J. Allstot, "A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing",​ //IEEE Transactions on Circuits and Systems I-Regular Papers//, vol. 58, no. 5, pp. 860-867, May 2011. [[https://​ieeexplore.ieee.org/​document/​5661878|doi:​ 10.1109/​TCSI.2010.2090565]]   * S. Aniruddhan, Sudip Shekhar and David J. Allstot, "A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing",​ //IEEE Transactions on Circuits and Systems I-Regular Papers//, vol. 58, no. 5, pp. 860-867, May 2011. [[https://​ieeexplore.ieee.org/​document/​5661878|doi:​ 10.1109/​TCSI.2010.2090565]]
   * S. Pavan, "On Continuous-Time $\Delta\Sigma$ Modulators With Return-to-Open DACs," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 58, no. 5, pp. 284-288, May 2011. [[https://​ieeexplore.ieee.org/​document/​5771064|doi:​ 10.1109/​TCSII.2011.2124930]]   * S. Pavan, "On Continuous-Time $\Delta\Sigma$ Modulators With Return-to-Open DACs," //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 58, no. 5, pp. 284-288, May 2011. [[https://​ieeexplore.ieee.org/​document/​5771064|doi:​ 10.1109/​TCSII.2011.2124930]]
-  * Nagendra Krishnapura,​ Abhishek Agrawaland Sameer Singh, "A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 58, no. 4, pp. 205-209, April 2011. [[https://​ieeexplore.ieee.org/​document/​5751658|doi:​ 10.1109/​TCSII.2011.2124571]] ​+  * Nagendra Krishnapura,​ Abhishek Agrawal and Sameer Singh, "A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps,"​ //IEEE Transactions on Circuits and Systems II: Express Briefs//, vol. 58, no. 4, pp. 205-209, April 2011. [[https://​ieeexplore.ieee.org/​document/​5751658|doi:​ 10.1109/​TCSII.2011.2124571]] ​
   * Nagendra Krishnapura,​ "​Electronic time stretching for fast digitization,"​ //2011 IEEE International Symposium of Circuits and Systems (ISCAS)//, Rio de Janeiro, 2011, pp. 1391-1394. [[https://​ieeexplore.ieee.org/​document/​5937832|doi:​ 10.1109/​ISCAS.2011.5937832]]   * Nagendra Krishnapura,​ "​Electronic time stretching for fast digitization,"​ //2011 IEEE International Symposium of Circuits and Systems (ISCAS)//, Rio de Janeiro, 2011, pp. 1391-1394. [[https://​ieeexplore.ieee.org/​document/​5937832|doi:​ 10.1109/​ISCAS.2011.5937832]]
   * S. Pavan, "The Inconvenient Truth about Alias Rejection in Continuous-time Delta-Sigma Modulators",​ //2011 IEEE International Symposium of Circuits and Systems (ISCAS)//, Rio de Janeiro, 2011, pp. 526-529. [[https://​ieeexplore.ieee.org/​document/​5937618|doi:​ 10.1109/​ISCAS.2011.5937618]]   * S. Pavan, "The Inconvenient Truth about Alias Rejection in Continuous-time Delta-Sigma Modulators",​ //2011 IEEE International Symposium of Circuits and Systems (ISCAS)//, Rio de Janeiro, 2011, pp. 526-529. [[https://​ieeexplore.ieee.org/​document/​5937618|doi:​ 10.1109/​ISCAS.2011.5937618]]
-  * A. Cicalini, S. Aniruddhan, R. Apte, F. Bossu, O. Choksi, D. Filipovic, K. Godbole, T.P. Hung, C. Komninakis, D. Maldonado, C. Narathong, B. Nejati, D. O'​Shea,​ X. QuanR. Rangarajan, J. Sankaranarayanan,​ A. See, R. Sridhara, B. SunW. SuK. van Zalinge, G. Zhang and K. Sahota, “A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver,​ digital baseband and multimedia processor,"​ //2011 IEEE International Solid-State Circuits Conference//,​ San Francisco, CA, 2011, pp. 368-370. [[https://​ieeexplore.ieee.org/​document/​5746357|doi:​ 10.1109/​ISSCC.2011.5746357]]+  * A. Cicalini, S. Aniruddhan, R. Apte, F. Bossu, O. Choksi, D. Filipovic, K. Godbole, T.P. Hung, C. Komninakis, D. Maldonado, C. Narathong, B. Nejati, D. O'​Shea,​ X. QuanR. Rangarajan, J. Sankaranarayanan,​ A. See, R. Sridhara, B. SunW. SuK. van Zalinge, G. Zhang and K. Sahota, “A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver,​ digital baseband and multimedia processor,"​ //2011 IEEE International Solid-State Circuits Conference//,​ San Francisco, CA, 2011, pp. 368-370. [[https://​ieeexplore.ieee.org/​document/​5746357|doi:​ 10.1109/​ISSCC.2011.5746357]]
   * S. Pavan, "Alias Rejection of Continuous-Time $\Delta\Sigma$ Modulators With Switched-Capacitor Feedback DACs," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 58, no. 2, pp. 233-243, Feb. 2011. [[https://​ieeexplore.ieee.org/​abstract/​document/​5641628|doi:​ 10.1109/​TCSI.2010.2071930]]   * S. Pavan, "Alias Rejection of Continuous-Time $\Delta\Sigma$ Modulators With Switched-Capacitor Feedback DACs," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 58, no. 2, pp. 233-243, Feb. 2011. [[https://​ieeexplore.ieee.org/​abstract/​document/​5641628|doi:​ 10.1109/​TCSI.2010.2071930]]
   * R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, "A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW," //2011 IEEE Custom Integrated Circuits Conference (CICC)//, San Jose, CA, 2011, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​6055287|doi:​ 10.1109/​CICC.2011.6055287]]   * R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, "A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW," //2011 IEEE Custom Integrated Circuits Conference (CICC)//, San Jose, CA, 2011, pp. 1-4. [[https://​ieeexplore.ieee.org/​document/​6055287|doi:​ 10.1109/​CICC.2011.6055287]]
Line 187: Line 193:
   * S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre and P.K. Hanumolu, “A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique,​” //IEEE Journal of Solid-State Circuits//, Volume: 46, Issue: 12, pp 2772- 2783, Dec. 2011. [[https://​ieeexplore.ieee.org/​document/​6007147|doi:​ 10.1109/​JSSC.2011.2162921]]   * S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre and P.K. Hanumolu, “A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique,​” //IEEE Journal of Solid-State Circuits//, Volume: 46, Issue: 12, pp 2772- 2783, Dec. 2011. [[https://​ieeexplore.ieee.org/​document/​6007147|doi:​ 10.1109/​JSSC.2011.2162921]]
   * Q. Khan, S. Rao, D. Swank, A. Rao, W. McIntyre, S. Bang and P.K. Hanumolu, "A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control,"​ //2011 Proceedings of the ESSCIRC (ESSCIRC)//,​ Helsinki, 2011, pp. 439-442. [[https://​ieeexplore.ieee.org/​document/​6045001|doi:​ 10.1109/​ESSCIRC.2011.6045001]]   * Q. Khan, S. Rao, D. Swank, A. Rao, W. McIntyre, S. Bang and P.K. Hanumolu, "A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control,"​ //2011 Proceedings of the ESSCIRC (ESSCIRC)//,​ Helsinki, 2011, pp. 439-442. [[https://​ieeexplore.ieee.org/​document/​6045001|doi:​ 10.1109/​ESSCIRC.2011.6045001]]
-  * S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyreP.K. Hanumolu, “A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing,"​ //2011 IEEE International Solid-State Circuits Conference//,​ San Francisco, CA, 2011, pp. 238-240. [[https://​ieeexplore.ieee.org/​document/​5746300|doi:​ 10.1109/​ISSCC.2011.5746300]]+  * S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre ​and P.K. Hanumolu, “A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing,"​ //2011 IEEE International Solid-State Circuits Conference//,​ San Francisco, CA, 2011, pp. 238-240. [[https://​ieeexplore.ieee.org/​document/​5746300|doi:​ 10.1109/​ISSCC.2011.5746300]]
  
 ===== 2010 ===== ===== 2010 =====
-  * Janakiraman Viraraghavan,​ Bharadwaj AmruturV. Visvanathan,​ "​Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks,"​ //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems//, vol. 29, no. 7, pp. 1056-1069, July 2010. [[https://​ieeexplore.ieee.org/​abstract/​document/​5487472|doi:​ 10.1109/​TCAD.2010.2049059]]+  * Janakiraman Viraraghavan,​ Bharadwaj Amrutur ​and V. Visvanathan,​ "​Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks,"​ //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems//, vol. 29, no. 7, pp. 1056-1069, July 2010. [[https://​ieeexplore.ieee.org/​abstract/​document/​5487472|doi:​ 10.1109/​TCAD.2010.2049059]]
   * S. Pavan, "​Design Techniques for High-Performance Continuous-time Delta Sigma Conversion,"​ //half day tutorial at the European Solid State Circuits Conference//,​ Seville, Spain, 2010.   * S. Pavan, "​Design Techniques for High-Performance Continuous-time Delta Sigma Conversion,"​ //half day tutorial at the European Solid State Circuits Conference//,​ Seville, Spain, 2010.
   * S. Thyagarajan,​ S. Pavan and P. Sankar, "Low distortion active filters using the Gm-assisted OTA-RC technique,"​ //2010 Proceedings of ESSCIRC//, Seville, 2010, pp. 162-165. [[https://​ieeexplore.ieee.org/​document/​5619904|doi:​ 10.1109/​ESSCIRC.2010.5619904]]   * S. Thyagarajan,​ S. Pavan and P. Sankar, "Low distortion active filters using the Gm-assisted OTA-RC technique,"​ //2010 Proceedings of ESSCIRC//, Seville, 2010, pp. 162-165. [[https://​ieeexplore.ieee.org/​document/​5619904|doi:​ 10.1109/​ESSCIRC.2010.5619904]]
Line 213: Line 219:
   * Y.Darhwekar,​ R.Kumar, D.Sahu, S.Pavan, A.Lacchwani and S.Mukherjee, ​ "A digitally assisted baseband filter with 9MHz bandwidth and 0.3 dB IQ mismatch for a WLAN receiver chain,"​ //2009 IEEE International Symposium on Circuits and Systems (ISCAS)//, Taipei, 2009, pp. 261-264. [[https://​ieeexplore.ieee.org/​document/​5117735|doi:​ 10.1109/​ISCAS.2009.5117735]]   * Y.Darhwekar,​ R.Kumar, D.Sahu, S.Pavan, A.Lacchwani and S.Mukherjee, ​ "A digitally assisted baseband filter with 9MHz bandwidth and 0.3 dB IQ mismatch for a WLAN receiver chain,"​ //2009 IEEE International Symposium on Circuits and Systems (ISCAS)//, Taipei, 2009, pp. 261-264. [[https://​ieeexplore.ieee.org/​document/​5117735|doi:​ 10.1109/​ISCAS.2009.5117735]]
   * S.Saxena,​P.Sankar and S.Pavan, "​Automatic tuning of time constants in single bit continuous-time delta-sigma modulators,"​ //2009 IEEE International Symposium on Circuits and Systems//, Taipei, 2009, pp. 2257-2260. [[https://​ieeexplore.ieee.org/​document/​5118248|doi:​ 10.1109/​ISCAS.2009.5118248]]   * S.Saxena,​P.Sankar and S.Pavan, "​Automatic tuning of time constants in single bit continuous-time delta-sigma modulators,"​ //2009 IEEE International Symposium on Circuits and Systems//, Taipei, 2009, pp. 2257-2260. [[https://​ieeexplore.ieee.org/​document/​5118248|doi:​ 10.1109/​ISCAS.2009.5118248]]
-  * N.Krishnapura,​ V.Guptaand N.Agrawal, "​Compact lowpass ladder filters using tapped coils,"​ //2009 IEEE International Symposium on Circuits and Systems//, Taipei, 2009, pp. 53-56.) ​ [[https://​ieeexplore.ieee.org/​document/​5117683|doi:​ 10.1109/​ISCAS.2009.5117683]]+  * N.Krishnapura,​ V.Gupta and N.Agrawal, "​Compact lowpass ladder filters using tapped coils,"​ //2009 IEEE International Symposium on Circuits and Systems//, Taipei, 2009, pp. 53-56.) ​ [[https://​ieeexplore.ieee.org/​document/​5117683|doi:​ 10.1109/​ISCAS.2009.5117683]]
   * V. Vasudevan, "​Analysis of clock jitter in continuous-time quadrature bandpass sigma-delta modulators with NRZ pulses,"​ //2009 Ph.D. Research in Microelectronics and Electronics//,​ Cork, 2009, pp. 176-179. [[https://​ieeexplore.ieee.org/​document/​5201334|doi:​ 10.1109/​RME.2009.5201334]]   * V. Vasudevan, "​Analysis of clock jitter in continuous-time quadrature bandpass sigma-delta modulators with NRZ pulses,"​ //2009 Ph.D. Research in Microelectronics and Electronics//,​ Cork, 2009, pp. 176-179. [[https://​ieeexplore.ieee.org/​document/​5201334|doi:​ 10.1109/​RME.2009.5201334]]
   * T.Laxminidhi,​ V.Prasadu and S.Pavan, "​Widely Programmable High-Frequency Active RC Filters in CMOS Technology,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 56, no. 2, pp. 327-336, Feb. 2009.. [[https://​ieeexplore.ieee.org/​document/​4571106|doi:​ 10.1109/​TCSI.2008.2001759]]   * T.Laxminidhi,​ V.Prasadu and S.Pavan, "​Widely Programmable High-Frequency Active RC Filters in CMOS Technology,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 56, no. 2, pp. 327-336, Feb. 2009.. [[https://​ieeexplore.ieee.org/​document/​4571106|doi:​ 10.1109/​TCSI.2008.2001759]]
Line 231: Line 237:
   * Sudip Shekhar, Jeffrey S. Walling, S. Aniruddhan and David J. Allstot, "CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits,"​ //IEEE Journal of Solid-State Circuits//, vol. 43, no. 5, pp. 1177-1186, May 2008. [[https://​ieeexplore.ieee.org/​document/​4494670|doi:​ 10.1109/​JSSC.2008.920360]]   * Sudip Shekhar, Jeffrey S. Walling, S. Aniruddhan and David J. Allstot, "CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits,"​ //IEEE Journal of Solid-State Circuits//, vol. 43, no. 5, pp. 1177-1186, May 2008. [[https://​ieeexplore.ieee.org/​document/​4494670|doi:​ 10.1109/​JSSC.2008.920360]]
   * S. Pavan, "Power and area efficient high speed analog adaptive equalization,"​ //2008 IEEE International Symposium on Circuits and Systems//, Seattle, WA, 2008, pp. 3126-3129. [[https://​ieeexplore.ieee.org/​document/​4542120|doi:​ 10.1109/​ISCAS.2008.4542120]]   * S. Pavan, "Power and area efficient high speed analog adaptive equalization,"​ //2008 IEEE International Symposium on Circuits and Systems//, Seattle, WA, 2008, pp. 3126-3129. [[https://​ieeexplore.ieee.org/​document/​4542120|doi:​ 10.1109/​ISCAS.2008.4542120]]
-  * K. Balemarthy and S. Pavan, "​Signal Processing for Optical Fiber Communication",​ Tutorial at the National Conference on Communication,​ February 1-3, Bombay, India. [[publications:​ncc08_spavan.pdf|slides]]+  * K. Balemarthy and S. Pavan, "​Signal Processing for Optical Fiber Communication", ​//Tutorial at the National Conference on Communication//, February 1-3, Bombay, India. [[publications:​ncc08_spavan.pdf|slides]]
   * S. Pavan, N. Krishnapura,​ R. Pandarinathan and P. Sankar, "A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications,"​ //IEEE Journal of Solid-State Circuits//, vol. 43, no. 2, pp. 351-360, Feb. 2008. [[https://​ieeexplore.ieee.org/​document/​4444576|doi:​ 10.1109/​JSSC.2007.914263]]   * S. Pavan, N. Krishnapura,​ R. Pandarinathan and P. Sankar, "A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications,"​ //IEEE Journal of Solid-State Circuits//, vol. 43, no. 2, pp. 351-360, Feb. 2008. [[https://​ieeexplore.ieee.org/​document/​4444576|doi:​ 10.1109/​JSSC.2007.914263]]
   * S. Pavan and N. Krishnapura,​ "​Oversampling Analog-to-Digital Converter Design,"​ //21st International Conference on VLSI Design (VLSID 2008)//, Hyderabad, 2008, pp. 7-7. [[https://​ieeexplore.ieee.org/​document/​4450467|doi:​ 10.1109/​VLSI.2008.130]]   * S. Pavan and N. Krishnapura,​ "​Oversampling Analog-to-Digital Converter Design,"​ //21st International Conference on VLSI Design (VLSID 2008)//, Hyderabad, 2008, pp. 7-7. [[https://​ieeexplore.ieee.org/​document/​4450467|doi:​ 10.1109/​VLSI.2008.130]]
Line 244: Line 250:
   * T. Laxminidhi, V. Prasadu and S. Pavan, "A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS," //2007 IEEE Custom Integrated Circuits Conference//,​ San Jose, CA, 2007, pp. 683-686. [[https://​ieeexplore.ieee.org/​document/​4405824|doi:​ 10.1109/​CICC.2007.4405824]] ​   * T. Laxminidhi, V. Prasadu and S. Pavan, "A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS," //2007 IEEE Custom Integrated Circuits Conference//,​ San Jose, CA, 2007, pp. 683-686. [[https://​ieeexplore.ieee.org/​document/​4405824|doi:​ 10.1109/​CICC.2007.4405824]] ​
   * S. Pavan, N. Krishnapura,​ R. Pandarinathan and Prabu Sankar, "A 90μW 15-bit ΔΣ ADC for digital audio,"​ //ESSCIRC 2007 - 33rd European Solid-State Circuits Conference//,​ Munich, 2007, pp. 198-201. [[https://​ieeexplore.ieee.org/​document/​4430279|doi:​ 10.1109/​ESSCIRC.2007.4430279]]   * S. Pavan, N. Krishnapura,​ R. Pandarinathan and Prabu Sankar, "A 90μW 15-bit ΔΣ ADC for digital audio,"​ //ESSCIRC 2007 - 33rd European Solid-State Circuits Conference//,​ Munich, 2007, pp. 198-201. [[https://​ieeexplore.ieee.org/​document/​4430279|doi:​ 10.1109/​ESSCIRC.2007.4430279]]
-  * S. Pavan and T. Laxminidhi, "​Accurate Characterization of Integrated Continuous-Time Filters,"​ //IEEE Journal of Solid-State Circuits//, vol. 42, no. 8, pp. 1758-1766, Aug. 2007. [[https://​ieeexplore.ieee.org/​document/​4277876|doi:​ 10.1109/​JSSC.2007.900288|+  * S. Pavan and T. Laxminidhi, "​Accurate Characterization of Integrated Continuous-Time Filters,"​ //IEEE Journal of Solid-State Circuits//, vol. 42, no. 8, pp. 1758-1766, Aug. 2007. [[https://​ieeexplore.ieee.org/​document/​4277876|doi:​ 10.1109/​JSSC.2007.900288]]
   * K. N. Parashar and N. Chandrachoodan,​ "A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation,"​ //2007 International Conference on Field Programmable Logic and Applications//,​ Amsterdam, 2007, pp. 792-795. [[https://​ieeexplore.ieee.org/​document/​4380770|doi:​ 10.1109/​FPL.2007.4380770]]   * K. N. Parashar and N. Chandrachoodan,​ "A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation,"​ //2007 International Conference on Field Programmable Logic and Applications//,​ Amsterdam, 2007, pp. 792-795. [[https://​ieeexplore.ieee.org/​document/​4380770|doi:​ 10.1109/​FPL.2007.4380770]]
   * T. Laxminidhi and S. Pavan, "​Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 54, no. 7, pp. 1481-1488, July 2007. [[https://​ieeexplore.ieee.org/​document/​4268410|doi:​ 10.1109/​TCSI.2007.899625]]   * T. Laxminidhi and S. Pavan, "​Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 54, no. 7, pp. 1481-1488, July 2007. [[https://​ieeexplore.ieee.org/​document/​4268410|doi:​ 10.1109/​TCSI.2007.899625]]
Line 262: Line 268:
   * S. Pavan and T.Laxminidhi,​ "A 70-500+MHz Programmable CMOS Filter Compensated for MOS Nonquasistatic Effects,"​ //2006 Proceedings of the 32nd European Solid-State Circuits Conference//,​ Montreux, 2006, pp. 328-331. [[https://​ieeexplore.ieee.org/​document/​4099770|doi:​ 10.1109/​ESSCIR.2006.307597]]   * S. Pavan and T.Laxminidhi,​ "A 70-500+MHz Programmable CMOS Filter Compensated for MOS Nonquasistatic Effects,"​ //2006 Proceedings of the 32nd European Solid-State Circuits Conference//,​ Montreux, 2006, pp. 328-331. [[https://​ieeexplore.ieee.org/​document/​4099770|doi:​ 10.1109/​ESSCIR.2006.307597]]
   * S. Murali and S. Pavan, "Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A,"​ //IEEE Custom Integrated Circuits Conference 2006//, San Jose, CA, 2006, pp. 201-204. [[https://​ieeexplore.ieee.org/​document/​4114939|doi:​ 10.1109/​CICC.2006.320910]]   * S. Murali and S. Pavan, "Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A,"​ //IEEE Custom Integrated Circuits Conference 2006//, San Jose, CA, 2006, pp. 201-204. [[https://​ieeexplore.ieee.org/​document/​4114939|doi:​ 10.1109/​CICC.2006.320910]]
-  * Ponnmozhi S. and Nitin Chandrachoodan,​ "​Design of Hardware Coprocessor for OTDR Application",​ 11th IEEE VLSI Design and Test Symposium, VDAT 2006, Goa, India, August 2006.+  * Ponnmozhi S. and Nitin Chandrachoodan,​ "​Design of Hardware Coprocessor for OTDR Application", ​//11th IEEE VLSI Design and Test Symposium//, VDAT 2006, Goa, India, August 2006.
   * S. Shekhar, S. Aniruddhan and D.J. Allstot, "A fully-differential CMOS Clapp VCO for IEEE 802.11a applications,"​ //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-. [[https://​ieeexplore.ieee.org/​document/​1693316|doi:​ 10.1109/​ISCAS.2006.1693316]]   * S. Shekhar, S. Aniruddhan and D.J. Allstot, "A fully-differential CMOS Clapp VCO for IEEE 802.11a applications,"​ //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-. [[https://​ieeexplore.ieee.org/​document/​1693316|doi:​ 10.1109/​ISCAS.2006.1693316]]
-+  ​* S. Aniruddhan, S. Shekhar and D.J. Allstot, "A delay generation technique for fast-locking frequency synthesizers,"​ //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-5466. [[https://​ieeexplore.ieee.org/​document/​1693870|doi:​ 10.1109/​ISCAS.2006.1693870]]+  ​* S. Aniruddhan, S. Shekhar and D.J. Allstot, "A delay generation technique for fast-locking frequency synthesizers,"​ //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-5466. [[https://​ieeexplore.ieee.org/​document/​1693870|doi:​ 10.1109/​ISCAS.2006.1693870]]
   * A. Sharma and S. Pavan, "A single inductor multiple output converter with adaptive delta current mode control,"​ //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-. [[https://​ieeexplore.ieee.org/​document/​1693915|doi:​ 10.1109/​ISCAS.2006.1693915]]   * A. Sharma and S. Pavan, "A single inductor multiple output converter with adaptive delta current mode control,"​ //2006 IEEE International Symposium on Circuits and Systems//, Island of Kos, 2006, pp. 4 pp.-. [[https://​ieeexplore.ieee.org/​document/​1693915|doi:​ 10.1109/​ISCAS.2006.1693915]]
   * K. Reddy and S. Pavan, "​Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 54, no. 10, pp. 2184-2194, Oct. 2007. [[https://​ieeexplore.ieee.org/​document/​4346678|doi:​ 10.1109/​TCSI.2007.905648]]   * K. Reddy and S. Pavan, "​Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 54, no. 10, pp. 2184-2194, Oct. 2007. [[https://​ieeexplore.ieee.org/​document/​4346678|doi:​ 10.1109/​TCSI.2007.905648]]
Line 281: Line 287:
   * K.N.Vikram and V.Vasudevan,​ "​Hardware-software co-simulation of bus-based reconfigurable systems",​ //​Microprocessors and Microsystems//,​ vol. 29(4), pp 133-144, May 2005. [[https://​www.sciencedirect.com/​science/​article/​abs/​pii/​S0141933104000924|doi:​ 10.1016/​j.micpro.2004.07.004]]   * K.N.Vikram and V.Vasudevan,​ "​Hardware-software co-simulation of bus-based reconfigurable systems",​ //​Microprocessors and Microsystems//,​ vol. 29(4), pp 133-144, May 2005. [[https://​www.sciencedirect.com/​science/​article/​abs/​pii/​S0141933104000924|doi:​ 10.1016/​j.micpro.2004.07.004]]
   * K.P.Sunil Rafeeque and V.Vasudevan,​ " A New Technique for on-chip error estimation and reconfiguration of current steering digital to analog converters,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 52, no. 11, pp. 2348-2357, Nov. 2005. [[https://​ieeexplore.ieee.org/​document/​1528680|doi:​ 10.1109/​TCSI.2005.853587]]   * K.P.Sunil Rafeeque and V.Vasudevan,​ " A New Technique for on-chip error estimation and reconfiguration of current steering digital to analog converters,"​ //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 52, no. 11, pp. 2348-2357, Nov. 2005. [[https://​ieeexplore.ieee.org/​document/​1528680|doi:​ 10.1109/​TCSI.2005.853587]]
-  * N. Krishnapura,​ M. Barazande-Pour,​ Q. Chaudhry, J. Khoury, K. LakshmikumarA. Aggarwal, "A 5Gb/s NRZ transceiver with adaptive equalization for backplane transmission,"​ //ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference//,​ 2005., San Francisco, CA, 2005, pp. 60-585 Vol. 1. [[https://​ieeexplore.ieee.org/​document/​1493868|doi:​ 10.1109/​ISSCC.2005.1493868]] +  * N. Krishnapura,​ M. Barazande-Pour,​ Q. Chaudhry, J. Khoury, K. Lakshmikumar ​and A. Aggarwal, "A 5Gb/s NRZ transceiver with adaptive equalization for backplane transmission,"​ //ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference//,​ 2005., San Francisco, CA, 2005, pp. 60-585 Vol. 1. [[https://​ieeexplore.ieee.org/​document/​1493868|doi:​ 10.1109/​ISSCC.2005.1493868]] 
-  * S. Pavan and S. Shivappa, "​Analysis of Traveling Wave and Transversal Analog Adaptive Equalizers,"​ //2005 IEEE International Symposium on Circuits and Systems//, Kobe, 2005, pp. 5962-5965 Vol. 6. (slides) ​[[https://​ieeexplore.ieee.org/​document/​1465997|doi:​ 10.1109/​ISCAS.2005.1465997]]+  * S. Pavan and S. Shivappa, "​Analysis of Traveling Wave and Transversal Analog Adaptive Equalizers,"​ //2005 IEEE International Symposium on Circuits and Systems//, Kobe, 2005, pp. 5962-5965 Vol. 6. [[https://​ieeexplore.ieee.org/​document/​1465997|doi:​ 10.1109/​ISCAS.2005.1465997]]
   * S. Pavan, M. Tarsia, S. Kudszus and D. Pritzkau, "​Design considerations for Integrated Modulator Drivers in SiGe Technology,"​ //​International Journal of High Speed Electronics and Systems//, Vol. 15, No. 03, pp. 477-495 (2005). [[https://​www.worldscientific.com/​doi/​abs/​10.1142/​S0129156405003284|doi:​ 10.1142/​S0129156405003284]]   * S. Pavan, M. Tarsia, S. Kudszus and D. Pritzkau, "​Design considerations for Integrated Modulator Drivers in SiGe Technology,"​ //​International Journal of High Speed Electronics and Systems//, Vol. 15, No. 03, pp. 477-495 (2005). [[https://​www.worldscientific.com/​doi/​abs/​10.1142/​S0129156405003284|doi:​ 10.1142/​S0129156405003284]]
-  * D.J. Allstot, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar and K. Soumyanath, "​Circuit techniques for CMOS multiple-antenna transceivers,"​ 2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers//, Long Beach, CA, USA, 2005, pp. 225-228. [[https://​ieeexplore.ieee.org/​document/​1489639|doi:​ 10.1109/​RFIC.2005.1489639]] ​+  * D.J. Allstot, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar and K. Soumyanath, "​Circuit techniques for CMOS multiple-antenna transceivers," ​//2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers//, Long Beach, CA, USA, 2005, pp. 225-228. [[https://​ieeexplore.ieee.org/​document/​1489639|doi:​ 10.1109/​RFIC.2005.1489639]] ​
   * D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh and S. Shekhar,"​Recent advances and design trends in CMOS radio frequency integrated Circuits",​ //​International Journal of High Speed Electronics and Systems//, vol.15, no.2, pp 377-428, June 2005. [[https://​www.worldscientific.com/​doi/​abs/​10.1142/​9789812774583_0006|doi:​ 10.1142/​9789812774583_0006]]   * D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh and S. Shekhar,"​Recent advances and design trends in CMOS radio frequency integrated Circuits",​ //​International Journal of High Speed Electronics and Systems//, vol.15, no.2, pp 377-428, June 2005. [[https://​www.worldscientific.com/​doi/​abs/​10.1142/​9789812774583_0006|doi:​ 10.1142/​9789812774583_0006]]
   * V.Vasudevan,​ "​Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits,"​ //​Proceedings. 42nd Design Automation Conference//,​ 2005., Anaheim, CA, 2005, pp. 397-402. [[https://​ieeexplore.ieee.org/​document/​1510361|doi:​ 10.1145/​1065579.1065685]]   * V.Vasudevan,​ "​Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits,"​ //​Proceedings. 42nd Design Automation Conference//,​ 2005., Anaheim, CA, 2005, pp. 397-402. [[https://​ieeexplore.ieee.org/​document/​1510361|doi:​ 10.1145/​1065579.1065685]]
Line 352: Line 358:
   * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay,​ S. Pavan, J. Cancio and T. R. Viswanathan,​ "A dual-mode 700-Msamples/​s 6-bit 200-Msamples/​s 7-bit A/D converter in a 0.25-μm digital CMOS process",​ //IEEE Journal of Solid State Circuits//, December 2000. [[https://​link.springer.com/​chapter/​10.1007%2F978-1-4757-3198-9_2|doi:​10.1007/​978-1-4757-3198-9_2]]   * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay,​ S. Pavan, J. Cancio and T. R. Viswanathan,​ "A dual-mode 700-Msamples/​s 6-bit 200-Msamples/​s 7-bit A/D converter in a 0.25-μm digital CMOS process",​ //IEEE Journal of Solid State Circuits//, December 2000. [[https://​link.springer.com/​chapter/​10.1007%2F978-1-4757-3198-9_2|doi:​10.1007/​978-1-4757-3198-9_2]]
   * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay,​ S. Pavan, J. Cancio and T. R. Viswanathan,​ "A 700M Sample/s 6 b read channel A/D converter with 7 b servo mode," //2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)//,​ San Francisco, CA, USA, 2000, pp. 426-427. [[https://​ieeexplore.ieee.org/​document/​839844|doi:​ 10.1109/​ISSCC.2000.839844]]   * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay,​ S. Pavan, J. Cancio and T. R. Viswanathan,​ "A 700M Sample/s 6 b read channel A/D converter with 7 b servo mode," //2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)//,​ San Francisco, CA, USA, 2000, pp. 426-427. [[https://​ieeexplore.ieee.org/​document/​839844|doi:​ 10.1109/​ISSCC.2000.839844]]
-  * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay,​ S. Pavan, J. Cancio and T. R. Viswanathan,​ "A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS", Ninth Workshop on Advances in Analog Circuit Design, Tegernsee, Germany , April 2000. [[https://​link.springer.com/​chapter/​10.1007%2F978-1-4757-3198-9_2|doi:​10.1007/​978-1-4757-3198-9_2]]+  * K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay,​ S. Pavan, J. Cancio and T. R. Viswanathan,​ "A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS", ​//Ninth Workshop on Advances in Analog Circuit Design//, Tegernsee, Germany , April 2000. [[https://​link.springer.com/​chapter/​10.1007%2F978-1-4757-3198-9_2|doi:​10.1007/​978-1-4757-3198-9_2]]
   * N. Krishnapura and P. Kinget, "A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS," //IEEE Journal of Solid-State Circuits//, vol. 35, no. 7, pp. 1019-1024, July 2000. [[https://​ieeexplore.ieee.org/​document/​848211|doi:​ 10.1109/​4.848211]]   * N. Krishnapura and P. Kinget, "A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS," //IEEE Journal of Solid-State Circuits//, vol. 35, no. 7, pp. 1019-1024, July 2000. [[https://​ieeexplore.ieee.org/​document/​848211|doi:​ 10.1109/​4.848211]]
   * N. Krishnapura,​ Y. Tsividis and D. R. Frey, "​Simplified technique for syllabic companding in log-domain filters,"​ //​Electronics Letters//, vol. 36, no. 15, pp. 1257-1259, 20 July 2000. [[https://​ieeexplore.ieee.org/​document/​856190|doi:​ 10.1049/​el:​20000978]]   * N. Krishnapura,​ Y. Tsividis and D. R. Frey, "​Simplified technique for syllabic companding in log-domain filters,"​ //​Electronics Letters//, vol. 36, no. 15, pp. 1257-1259, 20 July 2000. [[https://​ieeexplore.ieee.org/​document/​856190|doi:​ 10.1049/​el:​20000978]]
Line 366: Line 372:
   * S. Pavan, Y. Tsividis and K. Nagaraj, "A 60-350 MHz programmable analog filter in a digital CMOS process,"​ //​Proceedings of the 25th European Solid-State Circuits Conference//,​ Duisburg, Germany, 1999, pp. 46-49. [[https://​ieeexplore.ieee.org/​document/​1471092|Paper]]   * S. Pavan, Y. Tsividis and K. Nagaraj, "A 60-350 MHz programmable analog filter in a digital CMOS process,"​ //​Proceedings of the 25th European Solid-State Circuits Conference//,​ Duisburg, Germany, 1999, pp. 46-49. [[https://​ieeexplore.ieee.org/​document/​1471092|Paper]]
   * S. Pavan, Y. Tsividis and K. Nagaraj, "​Modeling of accumulation MOS capacitors for analog design in digital VLSI processes,"​ //1999 IEEE International Symposium on Circuits and Systems (ISCAS)//, Orlando, FL, 1999, pp. 202-205 vol.6. [[https://​ieeexplore.ieee.org/​document/​780130|doi:​ 10.1109/​ISCAS.1999.780130]]   * S. Pavan, Y. Tsividis and K. Nagaraj, "​Modeling of accumulation MOS capacitors for analog design in digital VLSI processes,"​ //1999 IEEE International Symposium on Circuits and Systems (ISCAS)//, Orlando, FL, 1999, pp. 202-205 vol.6. [[https://​ieeexplore.ieee.org/​document/​780130|doi:​ 10.1109/​ISCAS.1999.780130]]
-  * D.V.R. Murthy, S. Ramachandran and S. Srinivasan, "​Parallel implementation of 2D-discrete cosine transform using EPLDs,"​ Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013),​ Goa, India, 1999, pp. 336-339. [[https://​ieeexplore.ieee.org/​document/​745178|doi:​ 10.1109/​ICVD.1999.745178]]+  * D.V.R. Murthy, S. Ramachandran and S. Srinivasan, "​Parallel implementation of 2D-discrete cosine transform using EPLDs," ​//Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)//, Goa, India, 1999, pp. 336-339. [[https://​ieeexplore.ieee.org/​document/​745178|doi:​ 10.1109/​ICVD.1999.745178]]
   * S.Ramachandran,​ S.Srinivasan and R.Chen, "​EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression,"​ //1999 IEEE International Symposium on Circuits and Systems (ISCAS)//, Orlando, FL, 1999, pp. 375-378 vol.3. [[https://​ieeexplore.ieee.org/​document/​778863|doi:​ 10.1109/​ISCAS.1999.778863]]   * S.Ramachandran,​ S.Srinivasan and R.Chen, "​EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression,"​ //1999 IEEE International Symposium on Circuits and Systems (ISCAS)//, Orlando, FL, 1999, pp. 375-378 vol.3. [[https://​ieeexplore.ieee.org/​document/​778863|doi:​ 10.1109/​ISCAS.1999.778863]]
   * T.G.Venkatesh and S.Srinivasan,​ "A pruning based fast rate control algorithm for MPEG coding,"​ //​Proceedings Third International Conference on Computational Intelligence and Multimedia Applications. ICCIMA'​99 (Cat. No.PR00300)//,​ New Delhi, India, 1999, pp. 403-407. [[https://​ieeexplore.ieee.org/​document/​798564|doi:​ 10.1109/​ICCIMA.1999.798564]]   * T.G.Venkatesh and S.Srinivasan,​ "A pruning based fast rate control algorithm for MPEG coding,"​ //​Proceedings Third International Conference on Computational Intelligence and Multimedia Applications. ICCIMA'​99 (Cat. No.PR00300)//,​ New Delhi, India, 1999, pp. 403-407. [[https://​ieeexplore.ieee.org/​document/​798564|doi:​ 10.1109/​ICCIMA.1999.798564]]
Line 372: Line 378:
  
 ===== 1998 ===== ===== 1998 =====
-  * L. Toth, Y. Tsividisand N. Krishnapura,​ "​Analysis of noise and interference in companding signal processors,"​ //1998 IEEE International Symposium on Circuits and Systems (ISCAS)//, Monterey, CA, 1998, pp. 143-146 vol.1. [[https://​ieeexplore.ieee.org/​document/​704209|doi:​ 10.1109/​ISCAS.1998.704209]] +  * L. Toth, Y. Tsividis and N. Krishnapura,​ "​Analysis of noise and interference in companding signal processors,"​ //1998 IEEE International Symposium on Circuits and Systems (ISCAS)//, Monterey, CA, 1998, pp. 143-146 vol.1. [[https://​ieeexplore.ieee.org/​document/​704209|doi:​ 10.1109/​ISCAS.1998.704209]] 
-  * L. Toth, Y. Tsividisand N. Krishnapura,​ "On the analysis of noise and interference in instantaneously companding signal processors,"​ //IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing//,​ vol. 45, no. 9, pp. 1242-1249, Sept. 1998. [[https://​ieeexplore.ieee.org/​document/​718591|doi:​ 10.1109/​82.718591]]+  * L. Toth, Y. Tsividis and N. Krishnapura,​ "On the analysis of noise and interference in instantaneously companding signal processors,"​ //IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing//,​ vol. 45, no. 9, pp. 1242-1249, Sept. 1998. [[https://​ieeexplore.ieee.org/​document/​718591|doi:​ 10.1109/​82.718591]]
   * N. Krishnapura,​ S. Pavan, C. Mathiazhagan and B. Ramamurthi, "A baseband pulse shaping filter for Gaussian minimum shift keying,"​ //1998 IEEE International Symposium on Circuits and Systems (ISCAS)//, Monterey, CA, 1998, pp. 249-252 vol.1. [[https://​ieeexplore.ieee.org/​document/​704333|doi:​ 10.1109/​ISCAS.1998.704333]]   * N. Krishnapura,​ S. Pavan, C. Mathiazhagan and B. Ramamurthi, "A baseband pulse shaping filter for Gaussian minimum shift keying,"​ //1998 IEEE International Symposium on Circuits and Systems (ISCAS)//, Monterey, CA, 1998, pp. 249-252 vol.1. [[https://​ieeexplore.ieee.org/​document/​704333|doi:​ 10.1109/​ISCAS.1998.704333]]
   * N. Krishnapura,​ Y. Tsividis, K. Nagaraj and K. Suyama, "​Companding switched capacitor filters,"​ //ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)//,​ Monterey, CA, 1998, pp. 480-483 vol.1. [[https://​ieeexplore.ieee.org/​document/​704507|doi:​ 10.1109/​ISCAS.1998.704507]]   * N. Krishnapura,​ Y. Tsividis, K. Nagaraj and K. Suyama, "​Companding switched capacitor filters,"​ //ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)//,​ Monterey, CA, 1998, pp. 480-483 vol.1. [[https://​ieeexplore.ieee.org/​document/​704507|doi:​ 10.1109/​ISCAS.1998.704507]]
   * S. Pavan and Y. Tsividis, "An analytical solution for a class of oscillators,​ and its application to filter tuning,"​ //IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications//,​ vol. 45, no. 5, pp. 547-556, May 1998. [[https://​ieeexplore.ieee.org/​document/​668866|doi:​ 10.1109/​81.668866]]   * S. Pavan and Y. Tsividis, "An analytical solution for a class of oscillators,​ and its application to filter tuning,"​ //IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications//,​ vol. 45, no. 5, pp. 547-556, May 1998. [[https://​ieeexplore.ieee.org/​document/​668866|doi:​ 10.1109/​81.668866]]
-  * S. Pavan and Y. Tsividis, "An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning",​ //IEEE Transactions on Circuits and Systems-I//,​ vol. 45, no. 9, pp. 1242-1249, May 1998. (paper) ​[[https://​ieeexplore.ieee.org/​document/​668866|doi:​ 10.1109/​81.668866]]+  * S. Pavan and Y. Tsividis, "An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning",​ //IEEE Transactions on Circuits and Systems-I//,​ vol. 45, no. 9, pp. 1242-1249, May 1998. [[https://​ieeexplore.ieee.org/​document/​668866|doi:​ 10.1109/​81.668866]]
   * S. Venkatesh and S. Srinvasan, "​Modified butterfly structure for efficient implementation of pruned fast cosine transform,"​ //​Electronics Letters//, vol. 34, no. 14, pp. 1383-1385, 9 July 1998. [[https://​ieeexplore.ieee.org/​document/​706082|doi:​ 10.1049/​el:​19980977]]   * S. Venkatesh and S. Srinvasan, "​Modified butterfly structure for efficient implementation of pruned fast cosine transform,"​ //​Electronics Letters//, vol. 34, no. 14, pp. 1383-1385, 9 July 1998. [[https://​ieeexplore.ieee.org/​document/​706082|doi:​ 10.1049/​el:​19980977]]
   * S. Srinivasan and B. Srikanth, "​Implementation Of A Fast Data Access Architecture For Two Dimensional Applications,​ //​International Conference on Computational Intelligence and Multimedia Applications//,​ Churchill, Australia, Feb 1998.   * S. Srinivasan and B. Srikanth, "​Implementation Of A Fast Data Access Architecture For Two Dimensional Applications,​ //​International Conference on Computational Intelligence and Multimedia Applications//,​ Churchill, Australia, Feb 1998.
Line 387: Line 393:
  
   * M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker and T. Sutton, "​Current measurments in switching regulators",​ US 9,755,518, September 5, 2017. [[https://​patents.google.com/​patent/​US9755518|US9755518B2]]   * M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker and T. Sutton, "​Current measurments in switching regulators",​ US 9,755,518, September 5, 2017. [[https://​patents.google.com/​patent/​US9755518|US9755518B2]]
-  * M. Bansal, Q. Khan and C. Shi, "​Average current mode control of multi-phase switching power converters, US 9,442,140, Sep. 13, 2016. [[https://​patents.google.com/​patent/​JP6185194B2/​en|JP6185194B2]] +  * M. Bansal, Q. Khan and C. Shi, "​Average current mode control of multi-phase switching power converters," ​US 9,442,140, Sep. 13, 2016. [[https://​patents.google.com/​patent/​JP6185194B2/​en|JP6185194B2]] 
-  * Qadeer A. Khan,​Sandeep Chaman Dhar,Joshua A. ZAZZERA,​Todd R. Sutton, "​Circuits and Methods for Driving Resonant Actuators", US 9,344,022, May 17, 2016. [[https://​patents.google.com/​patent/​WO2015038703A1|WO2015038703A1]] +  * Qadeer A. Khan,​Sandeep Chaman Dhar,Joshua A. ZAZZERA,​Todd R. Sutton, "​Circuits and Methods for Driving Resonant Actuators," ​US 9,344,022, May 17, 2016. [[https://​patents.google.com/​patent/​WO2015038703A1|WO2015038703A1]] 
-  * Davinder Aggarwal, Vibhor Jain and Janakiraman VIRARAGHAVAN,​ "​Automated design rule checking (DRC) test case generation", US 8,875,064, Oct 28, 2014. [[https://​patents.google.com/​patent/​US8875064B2/​en|US8875064B2]]+  * Davinder Aggarwal, Vibhor Jain and Janakiraman VIRARAGHAVAN,​ "​Automated design rule checking (DRC) test case generation," ​US 8,875,064, Oct 28, 2014. [[https://​patents.google.com/​patent/​US8875064B2/​en|US8875064B2]]
   * Davinder Aggarwal, Vaibhav A. RUPARELIA, Neha Singh and Janakiraman VIRARAGHAVAN,​ "​Generic design rule checking (DRC) test case extraction",​ US 9,292,652, Mar 22 2016. [[https://​patents.google.com/​patent/​US9292652|US9292652B2]]   * Davinder Aggarwal, Vaibhav A. RUPARELIA, Neha Singh and Janakiraman VIRARAGHAVAN,​ "​Generic design rule checking (DRC) test case extraction",​ US 9,292,652, Mar 22 2016. [[https://​patents.google.com/​patent/​US9292652|US9292652B2]]
   * C. Narathong and S. Aniruddhan, "​Multi-mode Configurable Transmitter Circuit",​ US 8,099,127, Jan. 17, 2012. [[https://​patents.google.com/​patent/​US8099127|US8099127B2]]   * C. Narathong and S. Aniruddhan, "​Multi-mode Configurable Transmitter Circuit",​ US 8,099,127, Jan. 17, 2012. [[https://​patents.google.com/​patent/​US8099127|US8099127B2]]
Line 399: Line 405:
   * D. Tripathi, G.K. Sidhartha, Q. Khan, K. Misri and S. Wadhwa, "PVT Variation Detection and Compensation Circuit",​ US 7446592, Nov. 4, 2008. [[https://​patents.google.com/​patent/​US7446592B2/​en|US7446592B2]]   * D. Tripathi, G.K. Sidhartha, Q. Khan, K. Misri and S. Wadhwa, "PVT Variation Detection and Compensation Circuit",​ US 7446592, Nov. 4, 2008. [[https://​patents.google.com/​patent/​US7446592B2/​en|US7446592B2]]
   * Q. Khan and G.K. Sidhartha, "​Sequence-independent Power-on Reset for Multi-Voltage Circuits",​ US 7432748, Oct. 7, 2008. [[https://​patents.google.com/​patent/​US7432748|US7432748B2]]   * Q. Khan and G.K. Sidhartha, "​Sequence-independent Power-on Reset for Multi-Voltage Circuits",​ US 7432748, Oct. 7, 2008. [[https://​patents.google.com/​patent/​US7432748|US7432748B2]]
-  * D. Tripathi ​and J. BanerjeeQ. Khan, "​Differential Receiver Circuit",​ US 7414462, Aug. 19, 2008. [[https://​patents.google.com/​patent/​US7414462|US7414462B2]]+  * D. TripathiJ. Banerjee ​and Q. Khan, "​Differential Receiver Circuit",​ US 7414462, Aug. 19, 2008. [[https://​patents.google.com/​patent/​US7414462|US7414462B2]]
   * Q. Khan, H. Fukazawa and T. Nandurkar, "​Charge Pump Circuit for High Side Drive Circuit and Driver Driving Voltage Circuit",​ US 7388422, Jun. 17, 2008. [[https://​patents.google.com/​patent/​US7388422B2/​en|US7388422B2]]   * Q. Khan, H. Fukazawa and T. Nandurkar, "​Charge Pump Circuit for High Side Drive Circuit and Driver Driving Voltage Circuit",​ US 7388422, Jun. 17, 2008. [[https://​patents.google.com/​patent/​US7388422B2/​en|US7388422B2]]
   * G. K. Sidhartha, Q. Khan, D. Tripathi, S. Wadhwa and K. Misri, "PVT Variation Detection and Compensation Circuit",​ US 7388419, Jun. 17, 2008. [[https://​patents.google.com/​patent/​US7388419|US7388419B2]]   * G. K. Sidhartha, Q. Khan, D. Tripathi, S. Wadhwa and K. Misri, "PVT Variation Detection and Compensation Circuit",​ US 7388419, Jun. 17, 2008. [[https://​patents.google.com/​patent/​US7388419|US7388419B2]]
-  * Isaac Shpantzer,​Michael Tseytlin,​Yaakov Achiam,Aviv Salamon,​Israel Smilanski,​Olga Ritterbush,​Pak Shing Cho,Li Guoliang,​Jacob Khurgin,​Yehouda Meiman,​Alper Demir,Peter Feldman,​Peter Kinget,​Nagendra Krishnapura,​Jaijeet Roychowdhury,​Joseph Schwarzwalder and Charles Sciabarra, "​System and method for code division multiplexed optical communication",​ US 7,167,651, Jan. 23, 2007. [[https://​patents.google.com/​patent/​US7167651|US7167651B2]]+  * Isaac Shpantzer, Michael Tseytlin, Yaakov Achiam, Aviv Salamon, Israel Smilanski, Olga Ritterbush, Pak Shing Cho, Li Guoliang, Jacob Khurgin, Yehouda Meiman, Alper Demir, Peter Feldman, Peter Kinget, Nagendra Krishnapura,​ Jaijeet Roychowdhury,​ Joseph Schwarzwalder and Charles Sciabarra, "​System and method for code division multiplexed optical communication",​ US 7,167,651, Jan. 23, 2007. [[https://​patents.google.com/​patent/​US7167651|US7167651B2]]
   * Q. Khan and D. Tripathi, "​Transmission Line Driver Circuit",​ US 7292073, Nov. 6, 2007. [[https://​patents.google.com/​patent/​US7292073|US7292073B2]]   * Q. Khan and D. Tripathi, "​Transmission Line Driver Circuit",​ US 7292073, Nov. 6, 2007. [[https://​patents.google.com/​patent/​US7292073|US7292073B2]]
   * D. Tripathi, Q. Khan and K. Misri, "​Transmission Line Driver",​ US 7187197, Mar. 6, 2007. [[https://​patents.google.com/​patent/​US7187197|US7187197B2]]   * D. Tripathi, Q. Khan and K. Misri, "​Transmission Line Driver",​ US 7187197, Mar. 6, 2007. [[https://​patents.google.com/​patent/​US7187197|US7187197B2]]
   * S. Wadhwa, Q. Khan, K. Misri and D. Muhury, "​Digital Clock Frequency Doubler",​ US 7132863, Nov. 7, 2006. [[https://​patents.google.com/​patent/​US7132863|US7132863B2]]   * S. Wadhwa, Q. Khan, K. Misri and D. Muhury, "​Digital Clock Frequency Doubler",​ US 7132863, Nov. 7, 2006. [[https://​patents.google.com/​patent/​US7132863|US7132863B2]]
   * Q. Khan, D. Tripathi and K. Misri, "High Voltage Level Converter Using Low Voltage Devices",​ US 7102410, Sep. 5, 2006. [[https://​patents.google.com/​patent/​US7102410B2/​en|US7102410B2]]   * Q. Khan, D. Tripathi and K. Misri, "High Voltage Level Converter Using Low Voltage Devices",​ US 7102410, Sep. 5, 2006. [[https://​patents.google.com/​patent/​US7102410B2/​en|US7102410B2]]
-  * Q. Khan, S. Wadhwa and K. Misri, Bandgap Reference Circuit, US 7084698, Aug. 1, 2006. [[https://​patents.google.com/​patent/​US7084698B2/​en|US7084698B2]]+  * Q. Khan, S. Wadhwa and K. Misri, ​"Bandgap Reference Circuit," ​US 7084698, Aug. 1, 2006. [[https://​patents.google.com/​patent/​US7084698B2/​en|US7084698B2]]
   * Q. Khan, S. Wadhwa and K. Misri, "​Bidirectional Level Shifter",​ US 7061299, Jun, 13, 2006. [[https://​patents.google.com/​patent/​US7061299B2/​en|US7061299B2]]   * Q. Khan, S. Wadhwa and K. Misri, "​Bidirectional Level Shifter",​ US 7061299, Jun, 13, 2006. [[https://​patents.google.com/​patent/​US7061299B2/​en|US7061299B2]]
   * Q. Khan, S. Wadhwa and K. Misri, "​Single Supply Level Shifter",​ US 7009424, Mar. 7, 2006. [[https://​patents.google.com/​patent/​US7009424B2/​en|US7009424B2]]   * Q. Khan, S. Wadhwa and K. Misri, "​Single Supply Level Shifter",​ US 7009424, Mar. 7, 2006. [[https://​patents.google.com/​patent/​US7009424B2/​en|US7009424B2]]
Line 426: Line 432:
   * P. Kinget and N. Krishnapura,​ "​Programmable Frequency Divider",​ US 6,281,721, Aug. 28, 2001. [[https://​patents.google.com/​patent/​US6281721B1/​en|US6281721B1]]   * P. Kinget and N. Krishnapura,​ "​Programmable Frequency Divider",​ US 6,281,721, Aug. 28, 2001. [[https://​patents.google.com/​patent/​US6281721B1/​en|US6281721B1]]
   * Yendluri Shanthi-Pavan,​ Krishnaswamy Nagaraj and Venugopal Gopinathan, "​Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation",​ US 5,945,889, 31 Aug. 1999. [[https://​patents.google.com/​patent/​US5945889A|US5945889A]]   * Yendluri Shanthi-Pavan,​ Krishnaswamy Nagaraj and Venugopal Gopinathan, "​Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation",​ US 5,945,889, 31 Aug. 1999. [[https://​patents.google.com/​patent/​US5945889A|US5945889A]]
 +