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- | * Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, and Shanthi Pavan, "Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezo Electric Energy Harvesting," IEEE Journal of Solid State Circuits,// (to appear). | + | * Ashwin Kumar R. S. and Nagendra Krishnapura, "A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter," //45th European Solid-State Circuits Conference//, Krakow, Poland, Sep. 2019. |
+ | * N. Krishnapura, A. N. Bhat, S. Mukherjee, K. A. Shrivastava and M. Bonu, "Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables," //IEEE Transactions on Circuits and Systems I: Regular Papers//, 2019. doi: 10.1109/TCSI.2019.2926143. | ||
+ | * S. Kumar, R. Goroju, D. K. Bhat, K. S. Rakshitdatta and N. Krishnapura, "Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs," //IEEE Transactions on Circuits and Systems I: Regular Papers//, 2019. doi: 10.1109/TCSI.2019.2926927. | ||
+ | * Shanthi Pavan and Raviteja Theertham, "Improved offline calibration of DAC errors in Delta Sigma data converters," // IEEE Transactions on Circuits and Systems: Express Briefs,// (to appear). | ||
+ | * Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, and Shanthi Pavan, "Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezo Electric Energy Harvesting," // IEEE Journal of Solid State Circuits,// (to appear). | ||
* Raviteja Theertham, Prasanth Kootala, Sujith Billa, and Shanthi Pavan, "A 24mW chopped CTDSM achieving 103.5dB SNDR and 107.5dB DR in a 250kHz bandwidth," // IEEE Symposium on VLSI Circuits, Kyoto, Japan //, June 2019. | * Raviteja Theertham, Prasanth Kootala, Sujith Billa, and Shanthi Pavan, "A 24mW chopped CTDSM achieving 103.5dB SNDR and 107.5dB DR in a 250kHz bandwidth," // IEEE Symposium on VLSI Circuits, Kyoto, Japan //, June 2019. | ||
- | * Raviteja Theertham and Shanthi Pavan, "Unified analysis, modeling, and simulation of chopping artifacts in continuous-time delta-sigma converters," // IEEE Transactions on Circuits and Systems: Regular Papers //, (to appear). | + | * Raviteja Theertham and Shanthi Pavan, "Unified analysis, modeling, and simulation of chopping artifacts in continuous-time delta-sigma converters," // IEEE Transactions on Circuits and Systems: Regular Papers //, August 2019. |
- | * Kishalay Dutta, Vinod Menezes and Shanthi Pavan, "Analysis and design of cyclic switched-capacitor DC-DC converters," // IEEE Transactions on Circuits and Systems: Regular Papers //, (to appear). | + | * Kishalay Dutta, Vinod Menezes and Shanthi Pavan, "Analysis and design of cyclic switched-capacitor DC-DC converters," // IEEE Transactions on Circuits and Systems: Regular Papers //, August 2019. |
* Saravana Manivannan and Shanthi Pavan, "Degradation of alias rejection in continuous-time bandpass delta-sigma converters due to weak loop filter nonlinearities," //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. | * Saravana Manivannan and Shanthi Pavan, "Degradation of alias rejection in continuous-time bandpass delta-sigma converters due to weak loop filter nonlinearities," //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. | ||
* Shanthi Pavan, "Simplified analysis of total integrated noise in passive switched-capacitor and N-path filters," //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. | * Shanthi Pavan, "Simplified analysis of total integrated noise in passive switched-capacitor and N-path filters," //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. |