This shows you the differences between two versions of the page.
|
iep2010:start [2010/12/24 10:35] |
iep2010:start [2010/12/24 10:35] (current) |
||
|---|---|---|---|
| Line 1: | Line 1: | ||
| + | ====== Mapping DSP algorithms to architectures ====== | ||
| + | The purpose of this instruction enhancement program was to cover topics related to mapping digital signal processing (DSP) algorithms to hardware and software based architectures. The course was conducted from Feb 22-26, 2010. The lecture notes and lab material are given below. | ||
| + | |||
| + | * Day 1 - {{iep2010:intro.pdf|Introduction}} - Properties of DSP, architecture concerns, overview of problems //(Nitin Chandrachoodan)// | ||
| + | * Lab 1 - Design of FIR filter and implementation on Spartan 3 board ({{iep2010:lab1.zip|}}) | ||
| + | * Day 2 - DSP Architectures //(T. G. Venkatesh)// | ||
| + | * Lab 2 - Design trade-offs in FIR filter synthesis ({{iep2010:lab2.zip|}}) | ||
| + | * Day 3 - Issues in multicore implementations //(C. P. Ravikumar)// | ||
| + | * Lab 3 - Demo on multi-core and DSP-FPGA partitioning //(Cranes software)// | ||
| + | * Day 4 | ||
| + | * {{iep2010:scheduling.pdf|Scheduling under resource constraints}} //(Nitin Chandrachoodan)// | ||
| + | * {{iep2010:da.pdf|Distributed Arithmetic}} //(K. Sridharan)// | ||
| + | * {{iep2010:cordic.pdf|The CORDIC algorithm}} //(K. Sridharan)// | ||
| + | * Day 5 - {{iep2010:hls.pdf|High Level Scheduling}} //(Shankar Balachandran)// | ||