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EE6361: Advanced Topics in VLSI (Jan 2019)
Instructors
Classroom
Schedule
T-slot - Friday (2:00 - 4:50 PM)
Evaluation
Assignments: 10%
Mid Term: 30%
Project : 20%
End Semester Exam: 40%
Course Objective
(Why we teach this course?)
Introduce students to some relevant advanced topics of current interest in academia and industry
Give the students a feel for research topics
Make students aware of work happening in industries, specifically in India
This course will cover three broad subjects:
SRAM design (Rahul Rao)
Embedded DRAM design (Janakiraman)
Emerging memories (PCM/ STT RAM) (Rahul + Janakiraman + Guest lecture)
Learning Objectives
(What the students should be able to do after the course)
Part 1- SRAM Design
Articulate memory hierarchy and the value proposition of SRAMs in the memory chain + utilization in current processors
Explain SRAM building blocks and peripheral operations and memory architecture (with physical arrangement)
Articulate commonly used SRAM cells (6T vs 8T), their advantages and disadvantages
Explain the operation of a non-conventional SRAM cells, and their limitations
Explain commonly used assist methods
Explain how variations impact memory cells
Part 2- eDRAM Design and Yield Analysis
Explain the working of a (e)DRAM and what Embedded means?
Explain the working of a feedback sense amplifier and modify existing designs to improve performance
Calculate the voltage levels of operation of various components for an eDRAM
Introduce stacked protect devices to reduce voltage stress of the WL driver
Class 1 (18 Jan 2019)
Memory hierarchy
Memory organization
Flip flop
6T SRAM basics
Class 2 (25 Jan 2019)
Class 3 (1 Feb 2019)
Split word line with single ended read
Assymetric cells
Decouple Read/Write Cells (8T Cells)
Regenerative Feedback
Lecture Slides
Class 4 (8 Feb 2019)
Class 5 (15 Feb 2019)
Class 6 (22 Feb 2019)
Class 7 (1 Mar 2019)
Class 8 (8 Mar 2019)
Class 9 (15 Mar 2019)
Basics of DRAM
Definition of Embedded
Requirement for short BLs in DRAMs
Transfer ratio
Retention time/ Refresh rate analysis
Power supplies required for eDRAM
Advantages of eDRAM over eSRAM
In class Quiz
eDRAM Lecture Slides (2018)
Class 10 (22 Mar 2019)
Barth, J. et al., “A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008. PDF
In class quiz
Course Project
SRAM based In Memory Compute circuit design to implement the Multiply Accumulate Operation
Reference papers
A. Biswas and A. P. Chandrakasan, “CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks,” in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 217-230, Jan. 2019. doi: 10.1109/JSSC.2018.2880918
M. Kang, S. K. Gonugondla, A. Patil and N. R. Shanbhag, “A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array,” in IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 642-655, Feb. 2018. doi: 10.1109/JSSC.2017.2782087
Class 11 (29 Mar 2019)
G. Fredeman et al., “A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016.
doi: 10.1109/JSSC.2015.2456873 PDF
In class quiz
Class 12 (5 Apr 2019)