====== EE6324: Phase-Locked Loops(Sep.-Dec. 2020) ======
===== Instructor =====
  * [[https://sites.google.com/a/ee.iitm.ac.in/ssaxena/|Saurabh Saxena]]

===== Classroom =====
  * Goggle Meet: https://meet.google.com/wvg-jbju-stf

===== Schedule =====
A slot(Mo 8-9; Tu 12-1; Th 11-12; Fr 10-11)

===== Course page on moodle =====
Registered students can login and see the course page at [[https://courses.iitm.ac.in/|https://courses.iitm.ac.in/]]. Resources, tutorials, exam schedules, discussion forum etc. can be accessed from the moodle page.

===== Teaching Assistants =====
Login to moodle at [[https://courses.iitm.ac.in/|https://courses.iitm.ac.in/]] to post questions and contact faculty.

===== Evaluation =====
  * Assignments (20%)
  * Quiz-I (20%)
  * Quiz-II (20%)
  * Project (20%)
  * End Sem. (20%)

===== Recorded lectures =====
The recorded lectures are available [[http://www.ee.iitm.ac.in/~nagendra/videolectures/doku.php?id=start|here]]. You can also find lectures from previous years at the same link. The NPTEL online course [[https://onlinecourses.nptel.ac.in/noc15_ee02/|Analog Circuits]] also covers a portion of the material. 

===== Course contents =====
 Topics include analog and digital integer-N phase-locked loops (PLLs). Building blocks include phase/frequency detectors, charge-pump, LC/ring-oscillators, multi-modulus frequency dividers, active/passive loop-filter, etc.

===== Objectives =====
To develop intuition behind frequency synthesizer design, learning mathematical basis behind operation, and realizing PLLs at architecture and transistor level.

===== References =====
  * F. Gardner, Phaselock Techniques, John Wiley & Sons, 2005.
  * W. Egan, Phase-Lock Basics, John Wiley & Sons, 2008.
  * R. Best, Phase-Locked Loops : Design, Simulation, and Applications, McGraw Hill, 2003.

===== Pre-requisites =====
  * [[http://www.ee.iitm.ac.in/videolectures/doku.php?id=ee3002_2015nk:start|Analog Circuits]]