This shows you the differences between two versions of the page.
|
ctsd_adc_90nm [2014/09/10 19:28] |
ctsd_adc_90nm [2014/09/10 19:28] (current) |
||
|---|---|---|---|
| Line 1: | Line 1: | ||
| + | ====== 1V High-Speed, 14 Bit CTSD Modulator ( 90nm process)====== | ||
| + | [[design|go back to designs]] | ||
| + | |||
| + | |||
| + | ===== Problem Statement ===== | ||
| + | * Design of a 1V supply, 14-Bit, High-Speed Continuous-time Sigma-Delta Modulator in UMC90nm process. | ||
| + | * Achieve high Figure of Merit for the given design problem. | ||
| + | * Try adding Mash Architecture ( to support higher input signal Bandwidth by reducing OSR) | ||
| + | * Input Signal to be assumed as a wide-band signal. ie. significant level of out-of-band signals present | ||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | |||
| + | ===== Target specifications ===== | ||
| + | * 1.2V supply ( no supply variations assumed) | ||
| + | * 2.4Vp-p input signal full-scale amplitude | ||
| + | * 1kHz to 33MHz input signal Bandwidth | ||
| + | * Dynamic Range of 86 dB | ||
| + | * 20mW of power | ||
| + | |||
| + | |||
| + | ===== Architecture-level Constraints/targets ===== | ||
| + | * 1-Bit quantizer preferred | ||
| + | * CIFF sigma-delta loop to begin with | ||
| + | * Try-out Mash structure if possible | ||
| + | |||
| + | |||
| + | |||
| + | |||
| + | ====== Design Details ====== | ||
| + | *[[design_details#Architecture-level design details|Architecture-level design details]] | ||
| + | *[[design_details#Model-level simulation details|Model-level simulation details]] | ||
| + | *[[design_details#Process related data|Process related data]] | ||
| + | ***[[circuit_details#|Circuit Design details]]** | ||
| + | |||
| + | ====== Updates ====== | ||
| + | * [[design_details#updates| List of Tasks / issues and their status]] | ||
| + | | ||