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• Design of a 1V supply, 14-Bit, High-Speed Continuous-time Sigma-Delta Modulator in UMC90nm process.
• Achieve high Figure of Merit for the given design problem.
• Try adding Mash Architecture ( to support higher input signal Bandwidth by reducing OSR)
• Input Signal to be assumed as a wide-band signal. ie. significant level of out-of-band signals present

• 1.2V supply ( no supply variations assumed)
• 2.4Vp-p input signal full-scale amplitude
• 1kHz to 33MHz input signal Bandwidth
• Dynamic Range of 86 dB
• 20mW of power

• 1-Bit quantizer preferred
• CIFF sigma-delta loop to begin with
• Try-out Mash structure if possible

• Architecture-level design details
• Model-level simulation details
• Process related data
• Circuit Design details

• List of Tasks / issues and their status