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| + | ====== 10Gb/s transceiver for backplane transmission ====== | ||
| + | ==== Standard Document ==== | ||
| + | - {{:10gbasekr:P8023ap-D31.pdf|IEEE 802.3ap-complete standard}} | ||
| + | - {{:10gbasekr:10gbasekrphy.pdf|10GBase-KR transceiver and interconnect electrical specifications}} | ||
| + | - [[http://grouper.ieee.org/groups/802/3/ap/public/channel_model/index.html#Backplane%20Models|Backplane models]] | ||
| + | |||
| + | |||
| + | ==== References ==== | ||
| + | === General information on 10GBase-KR === | ||
| + | - John D'Ambrosia, [[http://www.commsdesign.com/showArticle.jhtml;jsessionid=QXIHYPPMZOL0EQSNDLRCKH0CJUNN2JVN?articleID=159902962|Driving 10-Gbit Serial ATCA Backplanes ]], CommsDesign. | ||
| + | - John D'Ambrosia, [[http://www.commsdesign.com/showArticle.jhtml;jsessionid=GQC1UCNF013T0QSNDLRCKH0CJUNN2JVN?articleID=164900591|Follow the road to signaling selection]], CommsDesign. | ||
| + | - John D'Ambrosia, [[http://www.commsdesign.com/showArticle.jhtml;jsessionid=GQC1UCNF013T0QSNDLRCKH0CJUNN2JVN?articleID=16502454|Getting a handle on fast backplanes]], CommsDesign. | ||
| + | - John D'Ambrosia, [[http://www.commsdesign.com/showArticle.jhtml;jsessionid=GQC1UCNF013T0QSNDLRCKH0CJUNN2JVN?articleID=49900228|Passive Channel Holds Key to 10-Gbit Backplanes]], CommsDesign. | ||
| + | |||
| + | === Transceivers === | ||
| + | - Bulzacchelli, J. F. et al., "{{:10gbasekr:04014602.pdf|A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology}}", IEEE Journal of Solid State Circuits, pp 2885-2900, vol. 41, no. 12, Dec. 2006.({{:10gbasekr:01696051.pdf|conference paper}}, {{:10gbasekr:V04_01.zip|slides}}) | ||
| + | - Kenney J. G. et al., "{{:10gbasekr:04014616.pdf|A 9.95–11.3-Gb/s XFP Transceiver in 0.13-μm CMOS}}", IEEE Journal of Solid State Circuits, pp 2901-2910, vol. 41, no. 12, Dec. 2006. | ||
| + | - Analui, B. et al., "{{10gbasekr:04014595.pdf|A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13-μm CMOS SOI Technology}}", IEEE Journal of Solid State Circuits, pp 2945-2955, vol. 41, no. 12, Dec. 2006. | ||
| + | - N. Krishnapura et al. "A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission", IEEE International Solid State Circuits Conference, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.({{http://www.ee.iitm.ac.in/~nagendra/papers/isscc2005_bpxcvr-pap.pdf|paper}}, {{http://www.ee.iitm.ac.in/~nagendra/papers/isscc2005_bpxcvr-sl.pdf|slides}}) | ||
| + | |||
| + | === Equalizers === | ||
| + | - Azita Emami, et al., "{{:10gbasekr:aida_jssc_apr07.pdf|Switched Capacitor Equalizer}} 90nm CMOS, JSSC,April 2007 | ||
| + | - Bulzacchelli, J. F. et al., "{{:10gbasekr:04014602.pdf|A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology}}", IEEE Journal of Solid State Circuits, pp 2885-2900, vol. 41, no. 12, Dec. 2006.({{:10gbasekr:01696051.pdf|conference paper}}, {{:10gbasekr:V04_01.zip|slides}}) | ||
| + | - N. Krishnapura et al. "A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission", IEEE International Solid State Circuits Conference, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.({{http://www.ee.iitm.ac.in/~nagendra/papers/isscc2005_bpxcvr-pap.pdf|paper}}, {{http://www.ee.iitm.ac.in/~nagendra/papers/isscc2005_bpxcvr-sl.pdf|slides}}) | ||
| + | - T. Beukema et al., {{:10gbasekr:2633beuk.pdf|"A 6.4-Gb/s CMOS SerDes Core With Feed-Forward and Decision-Feedback Equalization"}}, IEEE Journal of Solid State Circuits, pp 2633-2645, vol. 40, no. 12, Dec. 2005. | ||
| + | - R. Payne et al., {{:10gbasekr:2646payn.pdf|"A 6.25-Gb/s Binary Transceiver in 0.13-μm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels"}}, IEEE Journal of Solid State Circuits, pp 2646-2657, vol. 40, no. 12, Dec. 2005. | ||
| + | - J. Sewter and A. C. Carusone, {{:10gbasekr:1919sewt.pdf|"A 3-Tap FIR Filter With Cascaded Distributed Tap Amplifiers for Equalization Up to 40 Gb/s in 0.18-μm CMOS"}}, IEEE Journal of Solid State Circuits, pp 1919-1929, vol. 41, no. 8, Aug. 2006. | ||
| + | |||
| + | === Front End Amplifiers === | ||
| + | - S. Galal and B. Razavi, {{:10gbasekr:2138gala.pdf|"10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-μm CMOS Technology"}}, IEEE Journal of Solid State Circuits, pp 2138-2146, vol. 38, no. 12, Dec. 2003. | ||
| + | - Huang et al., {{:10gbasekr:04160073.pdf|"A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback"}}, IEEE Journal of Solid State Circuits, pp 1111-1120, vol. 42, no. 5, May 2007. | ||
| + | |||
| + | === Clock/data recovery circuits === | ||
| + | - [[http://www.omnisterra.com/walker/pubs.html|Link to Rick Walker's papers]] | ||
| + | - Nose K. et al., "{{:10gbasekr:04014625.pdf|A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling}}", IEEE Journal of Solid State Circuits, pp 2911-2920, vol. 41, no. 12, Dec. 2006. | ||
| + | - Kromer C. et al., "{{:10gbasekr:04014618.pdf|A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects}}", IEEE Journal of Solid State Circuits, pp 2921-2929, vol. 41, no. 12, Dec. 2006. | ||
| + | - Perrott, M. H. et al., "{{:10gbasekr:04014630.pdf|2.5-Gb/s Multi-Rate 0.25-μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition}}", IEEE Journal of Solid State Circuits, pp 2930-2944, vol. 41, no. 12, Dec. 2006. | ||
| + | |||
| + | === Mux/Demux Circuits === | ||
| + | - Tanabe et al., {{:10gbasekr:10gbps_8to1_mux_180nm.pdf|0.18-um CMOS 10-Gb/s Multiplexer/Demultiplexer | ||
| + | ICs Using Current Mode Logic with Tolerance to | ||
| + | Threshold Voltage Fluctuation}} | ||
| + | |||
| + | === Single ended and differential s-parameters === | ||
| + | - {{:10gbasekr:4hfan510.pdf|Single-Ended and Differential S-Parameters}}, Maxim application note. | ||
| + | |||
| + | |||
| + | ==== Process technology: TSMC 65nm CMOS ==== | ||
| + | === Documentation === | ||
| + | | /cad/library/tsmc65nm.old/PDK_doc/*.pdf | PDK usage guide | | ||
| + | | /cad/library/tsmc65nm/models/mixedSignal/current/CMN65GP V1d1_mismatch_models_released note.pdf | Mismatch model info | | ||
| + | | /cad/library/tsmc65nm/models/mixedSignal/current/CMN65GP_V1d1_stat_model_ release_ note.pdf | Statistical modeling info | | ||
| + | | /cad/library/tsmc65nm/models/mixedSignal/043007/TN65CMSP005_1_1.pdf | Device model info(Apr. 07) | | ||
| + | | /cad/library/tsmc65nm/ansoft/TN65CMSP008_1_0/Using Ansoft HFSS for TSMC UTM Inductors and ALRDL Inductors and Regular Metal Lines_65nm.pdf | Information for using Ansoft HFSS for inductor modeling. Also has interconnect thickness and dielectric info | | ||
| + | | /cad/library/tsmc65nm/models/mixedSignal/043007/doc_graphs/fitqual/MOSFET/lod_wpe/65Gplus_v1d0_LOD_WPE.ppt | | | ||
| + | | /cad/library/tsmc65nm/models/gplus/current/CLN65GPlus_V1d2_release_note.ppt | Model vs. meas. correlation | | ||
| + | | /cad/library/tsmc65nm_RF/PDK_doc/TSMC_DOC_WM/N65_PDK_rf_flow_guide_v0d1.pdf | RF design flow guide | | ||
| + | === Summary === | ||
| + | - MOS: Vtn = 0.2V-0.25V, Vtp=0.25V-0.3V | ||
| + | - Resistor: Non-silicided n+poly 130Ω/sq, Non-silicided p+poly 800Ω/sq, silicided n+poly 15Ω/sq, silicided p+poly 15Ω/sq | ||
| + | - A<sub>VTn</sub>=2.5mV·μm, A<sub>VTp</sub>=2.5mV·μm, A<sub>IDn</sub>=0.6%·μm, A<sub>IDp</sub>=0.6%·μm(There is some discrepancy between the tables and the figures. I have taken the worst case.) | ||
| + | - A<sub>rppolywo</sub>=1%·μm, A<sub>rnpolywo</sub>=4.7%·μm, A<sub>rppoly</sub>=1.6%·μm, A<sub>rnpoly</sub>=1.1%·μm | ||
| + | - Plots of key parameters(fT, gm, etc.) with temp. and process: {{:10gbasekr:mosplots.pdf|mosplots.pdf}} | ||
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| + | ==== Results ==== | ||
| + | === Front End Amplifiers and VGA === | ||
| + | {{:10gbasekr:frontend_amp.pdf|This file}} contains a decent documenatation on the important results of front end amplifier circuit. | ||
| + | == Res Loaded Diff pair == | ||
| + | Common mode : 700 mV. | ||
| + | ^ Corner (mos,res) ^Temperature ^DC-gain ^ 3-dB Bandwidth (GHz)^ | ||
| + | |ss| 0 | 31.6| 8.26| | ||
| + | |sf| 0| 25.7 | 12.4| | ||
| + | |fs|0| 31| 8.9| | ||
| + | |ff|0|25.2|13.5| | ||
| + | |tt|0|28.8| 10.2| | ||
| + | | ss | 100 | 30| 8.1| | ||
| + | |sf| 100| 23.5| 12| | ||
| + | |fs|100| 30 | 8.9| | ||
| + | |ff|100|24| 13.1| | ||
| + | |tt|100|27.2|10.2| | ||
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| + | |||
| + | |||
| + | == Important Plots == | ||
| + | The following plots have ac response under various gain settings in that particular corner. | ||
| + | * {{:10gbasekr:tt_0_gain_variation.ps|Typical MOS and res @ 0 C}} | ||
| + | * {{:10gbasekr:tt_100_gain_variation.ps|Typical MOS and res @ 100 C}} | ||
| + | * {{:10gbasekr:ss_0_gain_variation.ps|Slow MOS and high res @ 0 C}} | ||
| + | * {{:10gbasekr:ss_100_gain_variation.ps|Slow MOS and high res @ 100 C}} | ||
| + | * {{:10gbasekr:sf_0_gain_variation.ps|Slow MOS and low res @ 0 C}} | ||
| + | * {{:10gbasekr:sf_100_gain_variation.ps|Slow MOS and low res @ 100 C}} | ||
| + | * {{:10gbasekr:fs_0_gain_variation.ps|Fast MOS and high res @ 0 C}} | ||
| + | * {{:10gbasekr:fs_100_gain_variation.ps|Fast MOS and high res @ 100 C}} | ||
| + | * {{:10gbasekr:ff_0_gain_variation.ps|Fast MOS and low res @ 0 C}} | ||
| + | *{{:10gbasekr:ff_100_gain_variation.ps|Fast MOS and low res @ 100 C}} | ||
| + | |||
| + | ===Deserializer=== | ||
| + | {{:10gbasekr:demux_out.ps|Output wave}} | ||