Why this architecture ?:

Case 1: Consider a modulator with a MSA of -6dB. Inspite of the modulator having good SQNR at low signals, the modulator has lost 6dB dynamic range. If we can some how compress the input signal within the -6dB range by subtracting a digitally known analog signal from the input, we will be able to get back the lost signal. The digitally known signal can be ideally got using a nyquist rate crude flash-accurate DAC combination. By having a nyquist rate 2-level flash we can get back the 6dB dynamic range.

Case 2: Note that in case 1 we can feedback the feedback DAC and the feedforward DACs can be combined to be a 2-bit DAC. Since it is a multibit DAC we have the problem of DAC non-linearity. Since the DAC non-linearity problem is already there, going for multibit modulator will not make much difference. Since the multibit modulator have very high MSA, we can use this scheme to boost the modulator dynamic range with lesser power penalty.

Input signal has out-of-band signals also : In this case the feed forward flash has to work at much higher than nyquist rate to cancel all the signal that tend to saturate the modulator. So it would be required to put a low-pass filter at the modulator input which can reduces the out of band signal by 20dB atleast. Note that if this filter comes in signal path the noise of the filter will matter. So we can avoid adding any noise into the signal-band by having a feedforward low-pass filter architecture. |||rly, similarly to avoid saturation of the modulator due to the aliasing of out of band signals through the feedforward flash, a low pass filter has to be put on the flash path also. The feedforward low-pass filter architecture (as against conventional RC low-pass) can be used to critically match (which is a concern if the filter order is high) the Flash LP with the Modulator LP filter. Note that the aliasing is not a concern from SQNR point of view since it will be rejected by the modulator loop.

Slope error in the flash (even on band-limiting): Even if the i/p signal is band limited, it cant be compressed using a nyquist-rate flash within the LSB of the flash, because of the slope error. The 0dB signal at band-edge will have very high dV/dt, which the flash wont be able to follow. Because of this, the signal cant be compressed within the LSB of the flash. A 2-level flash has to run at 50 times the nyquist rate to compress the input signal within -5dB. Higher level flash will have to run at proportionally higher rates. So every 2X improvement in the dynamic range would need 4X higher power in the Flash.However we can still avoid this problem if we can introduce delay in the Modulator input-output path to cancel the flash delay accurately. Hence the flash can still work at nyquist rate

The peak amplitude of compressed signal (at the modulator o/p before feedforward summer) when the feedforward flash of OSR=OSR1,signal-band of Fin,flash comparator delay of Tt, excess-delay at the modulator i/p of Tds and modulator stf BW of BW_stf and order n can be intuitively shown by the following equation, ———–> |q1'|max=max(sin[2π(|1/OSR1+Fin*(Tt-Tds)|-Fin*n*/BW_stf)]+LSB/2 , LSB/2), if Ts=ORS1/Fin (flash1 sampling period)and T_stf=n/BW_stf (modulator delay) then, |q1'|max=max( sin[2π*Fin*(|Ts+Tt-Tds|- T_stf)]+LSB/2 , LSB/2). If we can make modulator path delay > feedforward flash path delay,then we can boost the overall modulator dynamic range by the dynamic range of the feedforward flash.

Avoid additional noise sources:The path from the ADC input to the modulator input summing node should not have any additional noise sources. The path includes a filter summing node, a delay compensating block and the modulator summing node. All these things have to be intelligently done using the input resistance itself with additional caps.

DAC linearity:One of the most critical component in this design is the DAC. The DAC has to be highly linear. There are several methods to overcome the non-linearity problem of the DAC. One of the method could be to digitally correct the codes using a digital non-linear block whose coefficients can be determined using a 1-bit,low speed sigma-delta calibration ADC.

Comparison with Multibit modulator and MASH:

Eventhough the problem of MSA (or the lower dynamic range)of single bit modulator can be overcome using a multibit modulator, the power consumption in the quantizer would be lot higher than the proposed architecture because the feedforward quantizer runs of much lower speed than the quantizer in the multibit modulator.

Eventhough the MASH also can be used to overcome similar problems, it comes with the power penalty of additional sigma-delta loop running at same speed as the modulator. Moreover, it is complicated by the use of a digital filter which needs to be matched with the analog filter. But the main advantage of MASH that the proposed architecture doesnt have is that the multibit DAC nonlinearity problem can be avoided in MASH.