Choice of Architecture

CIFF has higher integrator1 gain when compared to a CIFB equivalent. This allows lower size of the integrating cap and hence higher UGB for the OTA because of lower parasitic cap.

CIFF has only one DAC feedback point and hence less no of switches for current steering DAC.

In CIFF excess loop delay = integrator1 delay + summer delay + comparator delay. In CIFB excess loop delay = final-integrator delay + Comparator delay. It will take lesser power to make final-integrator fast than to make first integrator fast especially when the modulator dynamic ranges are higher. Hence CIFB will be prefered from excess loop delay point of view.

The first-integrator will have lower gain in CIFB and while higher gain in CIFF for a given swing limit, since the first-integrator will be in the fastest path in CIFF and while slowest path in CIFB. Higher gain means lower integrating cap and hence CIFF (or faster path for the first-integrator) may be preferred from this point of view.

From STF point of view, it is possible to get nth order Low-pass STF in case of nth order CIFB modulator by setting b2,b3…bn+1 coefficients 0. But CIFF gives only 1st order Low-pass STF.This is true only for Single input (no feedforward inputs) CIFF or CIFB. We can get desired STF by having distributed feedforward inputs irrespective of CIFF or CIFB architectures (ie.CIFF-IF and CIFB-IF)

Keeping above comparisons in mind, it will be optimal to keep the First-integrator neither in fastest path nor in the slowest path, but in an intermediate path (say (n-1)th order fastest path in an nth order modulator).

So a composite architecture with the combination of CIFF and CIFB should be used.

The Input signal to the Modulator is a wideband signal which may contain significant amount of out-of-band tones/noise.

The aliasing problem is eliminated by the CT modulator. But there is another problem that the input may now contain significant amount of Signal amplitude even though in-band signal power is very low. So modulator may saturate even without in-band signal. So either the modulator-input or the modulator-output should have low pass characteristics to make full use of the available modulator dynamic range. This can be done either by putting filter at modulator input or by making Modulator STF a low-pass filter.

Putting a filter (similar to anti alias filter) at the input will be power hungry because this filter has to be a low noise filter. It will be an additional noise contributer.

Making STF to be a low-pass filter can be easily done for conventional CIFF or CIFB architecture. But when going to the Compsite CIFF-CIFB architectures it will be difficult to map the coefficients from the conventional architecture to the composite architecture. So STF=1 will be the easiest alternative.

The filter requirement is lot less complicated when compared to an anti-alias filter since the out-of-band attenuation of 20dB will be good enough to nearly eliminate Modulator saturation by out-of-band signals. We can implement a Feedforward Low-pass filter to easily get 20dB kind of out-of-band attenuation and without adding any noise sources in the signal band. Therefore there is no noise spec for this filter and hence it will be less power hungry.

Ideally we would need 0dB MSA to support rail-2-rail input signal. But with single-Bit, 4th order, 64 OSR we may be able to support a pessimistic MSA of -6dB. Since the full scale itself will be VDD/2, all noise sources will have burn 4x more power to get back 6dB dynamic range.

Generally for high speed CT sigma delta ADC design, the motive will be to get the given dynamic range with a minimum OSR.

One alternative will be to go for Multibit quantizer. But it is seen that at high speeds multibit quantizer will be more power hungry than the first integrator itself. So the Multibit modulator is less attractive. But Companding Multibit quantizer could be a better alternative.

Mash structures would support higher order and lower OSR with good MSA to achieve a given dynamic range. Definitely this is ideal for High speed ADC. But the level of complexity involved in matching the analog loop filter and the digital filter (differentiator) makes this solution less attractive.

The simplest and less power hungry alternative will be to go for higher order,lower OSR, single-Bit architecture. But higher the order lesser will be the MSA. So if we can some how get back the dynamic range lost due to decreased MSA, of course without burning much power, we can buy this alternative. One way will be to use a companding quantizer. This alternative inspite of increasing the MSA, gives higher quantization noise/THD at higher inputs which may not be acceptible for all applications. Another alternative which we may think off will be to reduce the modulator i/p itself either by some digitally defined non-linearity or by a digitally known cancellation signal. This alternative will be discussed in detail in next sections.

Since we are using Single-bit quantizer (where the modulators clock jitter immunity is very less), we will have to use Switched-cap kind of DAC to get more immune to the clock jitter. This restricts us to go for RZ DAC feedback.

RZ DAC feedback gives additional benifit on excess delay immunity.

DAC feedback architecture will be defined precisely once Circuit design is started