Table of Contents

10Gb/s transceiver for backplane transmission

Standard Document

  1. IEEE 802.3ap-complete standard
  2. 10GBase-KR transceiver and interconnect electrical specifications
  3. Backplane models

References

General information on 10GBase-KR

  1. John D'Ambrosia, Driving 10-Gbit Serial ATCA Backplanes , CommsDesign.
  2. John D'Ambrosia, Follow the road to signaling selection, CommsDesign.
  3. John D'Ambrosia, Getting a handle on fast backplanes, CommsDesign.
  4. John D'Ambrosia, Passive Channel Holds Key to 10-Gbit Backplanes, CommsDesign.

Transceivers

  1. Bulzacchelli, J. F. et al., “A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology”, IEEE Journal of Solid State Circuits, pp 2885-2900, vol. 41, no. 12, Dec. 2006.(conference paper, slides)
  2. Kenney J. G. et al., “A 9.95–11.3-Gb/s XFP Transceiver in 0.13-μm CMOS”, IEEE Journal of Solid State Circuits, pp 2901-2910, vol. 41, no. 12, Dec. 2006.
  3. Analui, B. et al., “A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13-μm CMOS SOI Technology”, IEEE Journal of Solid State Circuits, pp 2945-2955, vol. 41, no. 12, Dec. 2006.
  4. N. Krishnapura et al. “A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission”, IEEE International Solid State Circuits Conference, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.(paper, slides)

Equalizers

  1. Azita Emami, et al., “Switched Capacitor Equalizer 90nm CMOS, JSSC,April 2007
  2. Bulzacchelli, J. F. et al., ”A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology“, IEEE Journal of Solid State Circuits, pp 2885-2900, vol. 41, no. 12, Dec. 2006.(conference paper, slides)
  3. N. Krishnapura et al. “A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission”, IEEE International Solid State Circuits Conference, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.(paper, slides)
  4. T. Beukema et al., "A 6.4-Gb/s CMOS SerDes Core With Feed-Forward and Decision-Feedback Equalization", IEEE Journal of Solid State Circuits, pp 2633-2645, vol. 40, no. 12, Dec. 2005.
  5. R. Payne et al., "A 6.25-Gb/s Binary Transceiver in 0.13-μm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels", IEEE Journal of Solid State Circuits, pp 2646-2657, vol. 40, no. 12, Dec. 2005.
  6. J. Sewter and A. C. Carusone, "A 3-Tap FIR Filter With Cascaded Distributed Tap Amplifiers for Equalization Up to 40 Gb/s in 0.18-μm CMOS", IEEE Journal of Solid State Circuits, pp 1919-1929, vol. 41, no. 8, Aug. 2006.

Front End Amplifiers

  1. S. Galal and B. Razavi, "10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-μm CMOS Technology", IEEE Journal of Solid State Circuits, pp 2138-2146, vol. 38, no. 12, Dec. 2003.
  2. Huang et al., "A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback", IEEE Journal of Solid State Circuits, pp 1111-1120, vol. 42, no. 5, May 2007.

Clock/data recovery circuits

  1. Link to Rick Walker's papers
  2. Nose K. et al., ”A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling“, IEEE Journal of Solid State Circuits, pp 2911-2920, vol. 41, no. 12, Dec. 2006.
  3. Kromer C. et al., ”A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects“, IEEE Journal of Solid State Circuits, pp 2921-2929, vol. 41, no. 12, Dec. 2006.
  4. Perrott, M. H. et al., ”2.5-Gb/s Multi-Rate 0.25-μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition“, IEEE Journal of Solid State Circuits, pp 2930-2944, vol. 41, no. 12, Dec. 2006.

Mux/Demux Circuits

  1. Tanabe et al., 0.18-um CMOS 10-Gb/s Multiplexer/Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation

Single ended and differential s-parameters

  1. Single-Ended and Differential S-Parameters, Maxim application note.

Process technology: TSMC 65nm CMOS

Documentation

/cad/library/tsmc65nm.old/PDK_doc/*.pdf PDK usage guide
/cad/library/tsmc65nm/models/mixedSignal/current/CMN65GP V1d1_mismatch_models_released note.pdf Mismatch model info
/cad/library/tsmc65nm/models/mixedSignal/current/CMN65GP_V1d1_stat_model_ release_ note.pdf Statistical modeling info
/cad/library/tsmc65nm/models/mixedSignal/043007/TN65CMSP005_1_1.pdf Device model info(Apr. 07)
/cad/library/tsmc65nm/ansoft/TN65CMSP008_1_0/Using Ansoft HFSS for TSMC UTM Inductors and ALRDL Inductors and Regular Metal Lines_65nm.pdf Information for using Ansoft HFSS for inductor modeling. Also has interconnect thickness and dielectric info
/cad/library/tsmc65nm/models/mixedSignal/043007/doc_graphs/fitqual/MOSFET/lod_wpe/65Gplus_v1d0_LOD_WPE.ppt
/cad/library/tsmc65nm/models/gplus/current/CLN65GPlus_V1d2_release_note.ppt Model vs. meas. correlation
/cad/library/tsmc65nm_RF/PDK_doc/TSMC_DOC_WM/N65_PDK_rf_flow_guide_v0d1.pdf RF design flow guide

Summary

  1. MOS: Vtn = 0.2V-0.25V, Vtp=0.25V-0.3V
  2. Resistor: Non-silicided n+poly 130Ω/sq, Non-silicided p+poly 800Ω/sq, silicided n+poly 15Ω/sq, silicided p+poly 15Ω/sq
  3. AVTn=2.5mV·μm, AVTp=2.5mV·μm, AIDn=0.6%·μm, AIDp=0.6%·μm(There is some discrepancy between the tables and the figures. I have taken the worst case.)
  4. Arppolywo=1%·μm, Arnpolywo=4.7%·μm, Arppoly=1.6%·μm, Arnpoly=1.1%·μm
  5. Plots of key parameters(fT, gm, etc.) with temp. and process: mosplots.pdf

Results

Front End Amplifiers and VGA

This file contains a decent documenatation on the important results of front end amplifier circuit.

Res Loaded Diff pair

Common mode : 700 mV.

Corner (mos,res) Temperature DC-gain 3-dB Bandwidth (GHz)
ss 0 31.6 8.26
sf 0 25.7 12.4
fs0 31 8.9
ff025.213.5
tt028.8 10.2
ss 100 30 8.1
sf 100 23.5 12
fs100 30 8.9
ff10024 13.1
tt10027.210.2
Important Plots

The following plots have ac response under various gain settings in that particular corner.

Deserializer

Output wave