====== Tips and Tricks ======




===== MATLAB Tricks =====
  * To invoke matlab6, in case you run out of matlab7 licenses, the matlab should be started by entering the following two commands in the terminal. 
    * UNSETENV LM_LICENSE_FILE 
    * /cad/tools/matlab6p1/bin/matlab
Matlab6 doesn't seem to start properly in the debain installed machines. The entire GUI doesn't work properly. But the command prompt, help, plots, matlab code editor work perfectly. The way to start matlab6 (for those machines alone) is to type the second command as  /cad/tools/matlab6p1/bin/matlab -nodesktop
  * Creating an inset within a figure [[http://kaisare.org/blog/?p=4|Creating Insets]]  
  * Getting presentation quality plots: Default font size and line thicknesses etc. are too small for presentations and even reports. You can set the default value of these(and whatever else you want to set when MATLAB starts) in ~/matlab/startup.m. See a sample {{startup.m|here}}. It is set for good presentation quality figures.
  * To include figures in LaTex, ''.eps'' or ''.pdf'' can be used. But if you won't be able to edit the figures. So save any figures you'd like to have for the future as matlab figures. This'll let you get back to it and edit if necessary.  

===== Keeping your designs accessible to others, but other files private =====
You can manually do ''chmod'', but that's a pain. At the beginning of your ''.cshrc'', put the line ''umask 077''. This will create files with permissions only to the user. To have files generated from, say, Cadence have read permissions for others, invoke it from inside a shell script with ''umask 022''. See the example ''myicms'' below.
<code>
#!/bin/csh
# 
# Create files with read permissions for others

umask 022
icms &

</code>




===== CADENCE Tricks =====
  * [[:cadence:corners|Corners analysis in Cadence]]
  * [[:cadence:montecarlo|Monte Carlo analysis in Cadence]]
  * __Cadence documentation setup__: Typing **cdsdoc** in command line or clicking **Help** in cadence brings up cdsdoc. The displayed books/chapters can be opened in the browser. To set up the browser, it needs to find Netscape/Mozilla and contact the localhost.
    * Make sure Mozilla/Firefox is in your path
    * Make a soft link named **netscape** to **mozilla** (ln -s /usr/bin/mozilla /usr/bin/netscape). My default browser is firefox, still, I could get things to work only by making this link
    * In the proxy setup, make sure that proxy is not used for your own machine(localhost, 127.0.0.1, machinename.domainname should be in the "do not use proxy for" list)
    * Try **cdsdoc -test** to see if it finds the docs and the browser. For more debugging, set the environment variable CDS_DEBUG_CDSDOC to "debug"
     * Make sure that the browser is open before trying out the help
    * Search in cdsdoc assumes that the term you enter is the complete word. Enclose it in wildcards if you don't get any matches. e.g. *envsetval* for all results on envsetval
  * Publication quality figures: Cadence figures are probably the ugliest you can have for reports etc. especially when they are exported from ''wavescan'' with default settings. ''AWD'' is marginally better. To improve the situation, in wavescan, you can go to Graph->Edit and choose white background, large bold fonts etc. By clicking on a curve, you can make the lines bold. You can then make this the default template by Graph->Template->Set current. This gives you figures that are legible(but are lacking aesthetics-for best results, import data into MATLAB and plot them)
  * ahdlcmi compile error: This can show up at the beginning of the simulation log file (''spectre.out'') when you use veriloga modules in your design. veriloga blocks are first compiled to ahdlcmi modules for quick simulations afterwards. If you get this error, you need to make the following softlink: ''sudo ln -s /lib/libc.so.6 /cad/tools/cadencetools/IC5141_ISR500.2.29/tools.lnx86/systemc/gcc/3.2.3/install/lib/libc.so''
  * ahdlcmi compile error: Following works for the 64-bit machines with debian OS : (1) Add commandline option -64 (if your machine is 64 bit)(2) The executable /bin/sh points to dash in many machines. Change the link to point  /bin/sh to bash.
  * Extracted parasitics: The script [[cadtools:caprep]] can be used to report parasitics between nets in capacitor-extracted views. Save the file and make it exectuable using "chmod +x caprep". Comparision of capacitor parasitics in differential circuits can also be done. Example usage is shown below:
<code cpp>
Report caps in sorted order on a particular net

Usage: ./caprep [-n net_name] [-c net_name1 net_name2] [-b net_name1 net_name2] [-f file] [-h]

 -n : Net name
 -c : Compare parasitics on 2 nets
 -b : Report parasitics between 2 nets
 -f : Input netlist file
 -h : Help

example1: ./caprep -n vip -f input.scs
example2: ./caprep -c vip vim -f input.scs
example3: ./caprep -b vip gnda -f input.scs
</code>
  * Digital synthesis: Abishek Goda's tutorial: http://10.7.7.58/wiki/syntut_avi.tar.bz2, http://10.7.7.58/wiki/syntut_flv.tar.bz2 [Some version of Mplayer has problem viewing the files showing a blue screen. It may also give a warning saying that "X11 error: BadAlloc (insufficient resources for operation)." In that case use the command 'mplayer -vo x11 encounter.avi']
  * NC Verilog: {{:cadence:multiplier_sim_using_ncverilog.pdf|NC Verilog usage example}}, {{:cadence:multiplier_sim_using_nclaunch.pdf|NC Launch usage example}}
  * Some useful Cadence tips: {{:cad_tips.pdf|On what to do when Cadence crashes suddenly... etc}}
  * Simulating cells without schematic when only their spice/spectre netlist is available: 
    * Create a symbol view for the cell with all the pins as in the .subckt in the netlist.
    * Edit the cdf of the cell (CIW -> Tools -> CDF -> edit). In the simulation information section fill the list of pins with each pin name enclosed in double-quotes. The order should match the order in the .subckt statement. e.g. “IN” “AVDD” “AVSS” “OUT”
    * In ADE, setup -> model library section : add the netlist as well
    * In ADE, setup -> environment : add the view symbol to both switch view list and stop view. Then simulate





===== CADENCE Bugs =====
  * **Weird FFT results**: If you get weird FFT results, i.e. "distortion" in a pure sine wave source(well above the numerical accuracy of -300dBc), you may be using a buggy release of spectre. To fix this, use the option "-format psfbin" in ADE environment. See {{adeoption.png|this figure}}. Details can be found at [[http://www.designers-guide.org/Forum/YaBB.pl?num=1277962510|this discussion thread]].
    * Details of the bug: After simulation with a certain strobeperiod, ocnPrint() gives the results where time points are truncated to one or two significant digits. The values though, do correspond to the correct timepoints. DFT seems to "interpolate" between the crudely truncated time points to the desired values, resulting in incorrect voltage/current values. This signal will obviously have a lot of distortion. 

  * **hierarchy editor not descending all the way to the bottom**: When a synthesized and P&Red design is imported into cadence using verilogIn, shadow views are not created properly and the hierarchy editor doesn't descend all the way down to the standard cells. [[See discussion at http://www.designers-guide.org/Forum/YaBB.pl?num=1310639460]]. This is due to a bug in some versions of IC5. To fix this, 
    - Change CDS_INST_DIR to /cad/tools/cadencetools/IC5141_ISR500.2.29; Start cadence and do verilog in. All shadow views are created properly with this version. 
    - Due to our license, this version cannot be used for simulations. Change CDS_INST_DIR back to /cad/tools/cadence and proceed with config view creation and simulations.

===== SPECTRE Tricks =====
==== Save and Plot ''oppoint'' of Spectre Transient Simulation ====
If you are interested in seeing various operating point values of devices plotted against time for a Spectre transient simulation, use following method (taken from SourceLink Solution No. 11003524) -
  * Tell Spectre to save the needed information by adding the correct save statement to the netlist. Say you are interested in plotting the operating information for a bipolar device name ''Q1'' in a block named ''osc''. Add the following statement to your netlist:

''save osc.Q1:oppoint''

   * To add a save statement in the Analog Design Environment you need to create a file, say ''myop.scs'', and add the line above into it. You can include the file by pointing out the file as a model using- Setup->Model Libraries in ADE.
  * After a successful Spectre transient simulation you can now plot the results from the Results Browser.
  * Similar procedure can be used for PSS and envelope analysis.


===== SPECTRE bugs =====
=== PSS + PAC Analysis in Circuits Using Inductors ===
       * Never use the 'Resistance' option in the inductor to set the inductor 'Q'.PAC analysis neglects the internal resistance of the inductor and treats it as ideal.
       * Rather use an external resistor in series with the inductor to set the 'Q'. 

=== PXF / PSS Analysis ===
       * Using ''highorder=yes'' MIC refinement option for PSS results in Segmentation Fault for the PXF analysis which follows this PSS analysis. (Spectre version 5.1.0)
       * Using ''highorder=no'' resolves the issue. 
           

===== XCircuit Tricks =====
  - Exporting any Matlab curve as a library object into Xcircuit
    * [[tips:xcircuit.m]] is the file which dumps out the library object corresponding to the matlab curve.
    * [[tips:test.m]] is an example where a sine wave is created for xcircuit.
    * In Xcircuit, use "File > Load New Library" to load the sine wave object dumped out in 'test.lps' by m/Calibre/LVS/G-DF-LOGIC_MIXED_MODE90N-1P9M-LOW_K_CALIBRE-LVS-1.1-P20.txt
===== Blackbox LVS ====
Blackbox LVS is useful for synthesized layouts (which don't have a transistor level schematic) or nonstandard components like inductors, varactors which are not from the PDK. The cell to be treated as a blackbox in LVS should have the correct pins(with pins M*_CAD TT in layout). It should have a dummy schematic with some component like a resistor or MOS inside connected to a pin. It doesn&rsquo;t matter what it is or where it is connected to.
In LVS options, specify the cells to be treated as blackboxes as shown below. Multiple cells can be specified on the same LVS BOX line or separate lines.

Insert picture ="/dokuwiki/_detail/cadtools/blackboxlvs.png?id=cadtools%3Acalibre&amp;cache=cache" class="media" title="cadtools:blackboxlvs.png"><img src="/dokuwiki/_media/cadtools/blackboxlvs.png

If the layout has more pins than the schematic, the LVS result will have only pin mismatch error. You can manually check for this and see that there are no other errors. Alternatively, you can remove the extra pins in the layout. This can happen with synthesized cells which have a huge number of pins inside. These can be selected together and converted to text layer. Only the pins on the periphery, which are the actual connections to the outside, can be retained. This process only checks for connections to the pins. What you have inside the cell is up to you. If you have metal line running over the cell which shorts out the insides, this method won&rsquo;t check it.


===== Extraction ====
<li class="level1"><div class="li"> Use <code>your_working_directory/pex</code> for PEX. </div>
</li>
<li class="level1"><div class="li"> Make a softlink to <code>/cad/library/UMCxxx/RuleDecks/Calibre/calview.cellmap</code> in your working directory</div>
</li>
<li class="level1"><div class="li"> Cancel the <code>runset</code> prompt the first time you use the tool</div>
</li>
<li class="level1"><div class="li"> Use <code>your_working_directory/pex</code> for PEX. </div>
</li>
<li class="level1"><div class="li"> Once you setup the rules file etc. you can store them as <code>pex.rules</code> runset file in your pex directory. This runset file can be loaded each time to give you the desired setup. </div>
</li>
<li class="level1"><div class="li"> Choose <strong>Export from Layout viewer</strong> and <strong>Export from Schematic viewer</strong> for layout and netlist inputs</div>
</li>
<li class="level1"><div class="li"> Choose <code>Setup&rarr;Show PEX options</code></div>
</li>
<li class="level1"><div class="li"> Enter appropriate power and ground nodes in <code>LVS options&rarr;Supply</code>. Name connections etc. can also be specified here.</div>
</li>
<li class="level1"><div class="li"> In <code>Outputs</code>, choose <code>CALIBREVIEW</code> for extracted view(similar to av_extracted) or <code>SPECTRE</code> to get only a netlist in spectre format.</div>
</li>
<li class="level1"><div class="li"> Your <code>Calibre View Setup</code> form should look as follows</div>
</li>
</ul>

<p>
  <a href="/dokuwiki/_detail/cadtools/calibrepex.png?id=cadtools%3Acalibre&amp;cache=cache" class="media" title="cadtools:calibrepex.png"><img src="/dokuwiki/_media/cadtools/calibrepex.png?w=400&amp;h=&amp;cache=cache" class="media" alt="" width="400" /></a>
</p>
<ul>
<li class="level1"><div class="li"> Parasitics can be viewed from <strong>RVE</strong>. Use <code>View&rarr;Net parasitics</code>. </div>
</li>
</ul>

</div>
<!-- SECTION [5685-6733] -->
<h3><a name="rules_files_same_as_for_lvs" id="rules_files_same_as_for_lvs">Rules files(same as for LVS)</a></h3>
<div class="level3">
<ul>
<li class="level1"><div class="li"> 180nm: <code>/cad/library/UMC180/RuleDecks/Calibre/LVS/G-DF-MIXED_MODE_RFCMOS18-1.8V_3.3V-1P6M-MMC_CALIBRE-LVS-2.0-P2.txt</code></div>
</li>
<li class="level1"><div class="li"> 130nm: <code>/cad/library/UMC130/RuleDecks/Calibre/LVS/G-DF-MIXED_MODE_RFCMOS13-1P8M-MMC-FSG-L130E-CALIBRE-LVS-2.3-P2.txt</code></div>
</li>
<li class="level1"><div class="li"> 90nm: (Both options below are available on different miniasic runs)</div>
<ul>
<li class="level2"><div class="li"> RF(3um thick top metal): <code>/cad/library/UMC90/RuleDecks/Calibre/LVS/G-DF-LOGIC_MIXED_MODE90N-1P9M-LOW_K_CALIBRE-LVS-1.1-P20.txt</code> (<em>Right now, the setup is the same as for 0.8um top metal; LVS should be correct; Top metal parasitics would be wrong. Calibre PEX gives errors with 3um metal specific file</em>)</div>
</li>
<li class="level2"><div class="li"> Logic(0.8um thick top metal): <code>/cad/library/UMC90/RuleDecks/Calibre/LVS/G-DF-LOGIC_MIXED_MODE90N-1P9M-LOW_K_CALIBRE-LVS-1.1-P20.txt</code></div>
</li>
</ul>
</li>
</ul>

</div>
<!-- SECTI

<li For LVS run in process offering multiple metal options (like UMC65,UMC90), the metal option needs to be set to appropriate one as allowed by latest miniasic offering. One issue observed due to not doing this is that the MIMCAP was not extracted properly in layout netlist and LVS fails. To set the metal option, uncomment the appropriate "#DEFINE" line in LVS rule file. For 65nm following was the line :
<code>#DEFINE TOP_METAL_ME9_1T1F1U // To switch LVS to 1P9M1T1F1U</code>
Also uncomment the already existing "#DEFINE" line (that sets metal option to different metal option)</li>

===== Printer tricks =====
==== Printing Multiple Pages Per Sheet ====

You can easily print multiple pages per sheet of paper. To do this, you must have a Postscript (PS) file of what you want to print or generate postscript from a command and send it to a pipe. The command to use to print multiple pages per sheet is psnup. There are many options, so you should read the manual page (man psnup) for more information. The psnup command acts as a filter, meaning it takes a PS file as input and sends a new PS file to its output. To print this output file you can send it to a file using something like:

# psnup -4 input.ps > output.ps

and then print the output.ps file using an appropriate lpr command. However, if you have no interest in retaining the output PS file, just use a pipe like this:

# psnup -4 input.ps | lpr

===== Eldo tricks ======
One can use [[tips:extract.pl]] to extract the data from chi file to plot using some other plotter (like gnuplot/matlab).Store this file as an executable. Run this program with the name of the chi file(e.g filter.chi) as the argument.
The variable name with V or I prefixing it, (depending on if its a voltage or a current plot), will be the name of the outputfile with .dat as extension.

# ./extract.pl filter.chi


===== Using VNC viewer =====

Using VNC gives you the ability to connect back to the session that you were running. It also survives broken connections etc. as long as the server is running properly.

The following steps must be followed: Although it is possible to directly connect to the server using vncviewer, it is recommended to use ssh tunnel as it is more secure, and can be faster because of compression. 

  - Log on to the computer of your choice (say ti1) using ''$> ssh username@ti1''
  - Start vncserver by using ''$> vncserver -depth 24 -geometry 1024x768'' [You need a depth of 24 for Cadence. Use the right geometry to suit your (client) screen size]
  - It'll say something like ''New 'vega.ee.iitm.ac.in:2 (nagendra)' desktop is vega.ee.iitm.ac.in:2'' Note the number after the colon, in this case ''02'', hereafter referred to as ''xx''. This corresponds to port ''59xx'' of the machine
  - From your local machine, do ''ssh -C -L 59yy:localhost:59xx username@ti1'' [''yy'' is arbitrary, but to avoid conflicts, use ''yy=xx+50''] This creates an encrypted tunnel between port ''59yy'' of the client machine and port ''59xx'' of the server. ''-C'' option compresses the traffic.
  - From your local machine, connect to port ''59yy'' of the local machine. using ''$> vncviewer localhost:yy'' or ''$> vncviewer localhost:59yy'' 
  - Go back to ti1, and issue ''$> vncserver -kill :xx''
  - A directory called .vnc will be created in your /home/username folder
  - To set gnome session as default, open the file ''/home/username/.vnc/xstartup'' and do the following changes -
  - Delete ''twm &'' and replace it with ''exec gnome-session &''; For kde replace ''twm &'' with ''startkde''
  - Repeat steps 1,2 to restart the vnc server
  - Repeat steps 3,4,5 to reconnect to the vnc server
  - After finishing your session, close the exported display using F8 key.
  - You can get back to this session as you left it using steps 3,4,5 from any machine. Open an ssh tunnel between port 59yy of your machine and 59xx of the server and connect vncviewer to ''localhost:59yy''
  - If you are done with the VNC session, terminate your session on ti1 by logging onto ti1 and using step 6. Don't do this if something is running on the vncserver and you want to access the results later
**
Grey screen problem in VNC**
If you find the grey screen in your vnc session, change your xstartup file located in .vnc folder. Uncomment "unset SESSION_MANAGER" and change "exec gnome-session &" to "gnome-session".

===== Generating a pdf document with all fonts embedded in it =====
If the fonts are not embedded in the file, the pdf looks different, sometimes drastically so, in different readers. Whenever you make documents for distribution: paper submission, theses, reports, you should embed all fonts so that there are no readability issues. To check whether they are embedded, open the pdf in Adobe Acroread, go to File->Properties and open the fonts tab. All fonts should be marked as embedded (subset). Since we write in latex, you need to convert from ps to pdf with all fonts embedded. 
  * From linux command line, do the following to convert filename.ps to filename.pdf with all fonts embedded \\
''gs -dSAFER -dNOPAUSE -dBATCH -sDEVICE=pdfwrite -sPAPERSIZE=a4 -dPDFSETTINGS=/printer -dCompatibilityLevel=1.4 -dMaxSubsetPct=100 -dSubsetFonts=true -dEmbedAll Fonts=true -sOutputFile=filename.pdf filename.ps''
  * It can also be done using ''gsview'' (installed on VLSI lab/TI lab machines) with the conversion options shown in {{:misc:pdf_conv_w_gs.pdf|this document}}. There is a large number of options, but you only have to set it once and gsview will remember it for you the next time. Set ''CompatibilityLevel'' to the highest available to be compliant with 5 "" "Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1)"
  * If you have Adobe (full version, not just the reader) installed, you can convert documents to pdf

To do: Figure out the option to put in kile for doing the above